AD9516-3 Analog Devices, AD9516-3 Datasheet - Page 13
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AD9516-3
Manufacturer Part Number
AD9516-3
Description
14-Output Clock Generator
Manufacturer
Analog Devices
Datasheet
1.AD9516-3.pdf
(84 pages)
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Parameter
TIMING
PD , SYNC , AND RESET PINS
Table 15.
Parameter
INPUT CHARACTERISTICS
RESET TIMING
SYNC TIMING
LD, STATUS, REFMON PINS
Table 16.
Parameter
OUTPUT CHARACTERISTICS
MAXIMUM TOGGLE RATE
ANALOG LOCK DETECT
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
LD PIN COMPARATOR
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CS to SCLK Setup and Hold, t
CS Minimum Pulse Width High, t
Output Voltage High (V
Output Voltage Low (V
Capacitance
Normal Range
Extended Range
Trip Point
Hysteresis
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
Pulse Width Low
Pulse Width Low
LO
HI
DH
SCLK
DS
OL
OH
)
)
)
Min
2.0
50
1.5
S
, t
DV
H
PWH
Typ
110
2
Max
0.8
1
Min
16
16
2
1.1
2
3
Min
2.7
1.02
8
Unit
V
V
μA
μA
pF
ns
High speed clock cycles
Typ
Typ
100
3
1.6
260
Rev. 0 | Page 13 of 84
Max
25
8
Max
0.4
Unit
V
V
MHz
pF
MHz
kHz
V
mV
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
These pins each have a 30 kΩ internal pull-up resistor
High speed clock is CLK input signal
Test Conditions/Comments
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs;
see Table 53, 0x17, 0x1A, and 0x1B
Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs may
couple to output when any of these pins are toggling
On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
Frequency above which the monitor indicates the
presence of the reference
Frequency above which the monitor indicates the
presence of the reference
Test Conditions/Comments
AD9516-3