ADP3804 Analog Devices, ADP3804 Datasheet - Page 7

• Manufacturer Part Number: ADP3804
• Description: High Frequency Switch Mode Li-Ion Battery Charger
• Manufacturer: Analog Devices

2.5 V Precision Reference
The voltage at the BAT pin is compared to an internal preci-
sion, low temperature drift reference of 2.5 V. The reference is
available externally at the REF pin. This pin should be by-
passed with a 100 pF capacitor to the analog ground pin,
AGND. The reference can be used as a precision voltage exter-
nally. However, the current draw should not be greater than
100 µA, and no noisy, switching type loads should be con-
nected.
6 V Regulator
The 6 V regulator supplies power to most of the analog cir-
cuitry on the ADP3804. This regulator should be bypassed to
AGND with a 10 nF capacitor. This reference has a 3 mA
source capability to power external loads if needed.
CCCV
An open drain output is available to signal when the ADP3804
switches from CC to CV charging. An external pull-up resistor
of 100 k to REG or other pull-up voltage is required for this
function. If the CCCV signal is not needed, the pin should be
left open. The CCCV function uses two comparators to moni-
tor the battery voltage and the charge current. In order for the
CCCV pin to go high, signaling CV mode, the battery voltage
must be higher than 95% of its final value, and the current
must be less than 80% of its programmed value. If the battery
voltage is less than 95% then CCCV will be low regardless of
the actual current flowing. This is to prevent a false output
during startup when the current is low.
System Current Sense
An uncommitted differential amplifier is provided for addi-
tional high side current sensing. This amplifier, AMP2, has a
fixed gain of 50 V/V from the SYS+ and SYS- pins to the ana-
log output at ISYS. ISYS has a 1 µA source capability to drive
an external load. The common mode range of the input pins is
from 4 V to VCC. This amplifier is the only part of the
ADP3804 that remains active during shutdown. The power to
this block is derived from the bias current on the SYS+ and
SYS- pins.
A separate comparator is included to provide a flag when the
voltage at ISYS rises above 2.5 V. The open drain output is
capable of sinking 1 µA when the threshold is exceeded. This
comparator is turned off during shutdown to conserve power.
Shutdown
A high impedance CMOS logic input is provided to turn off the
ADP3804. When the voltage on SD is less than 0.8 V, the
ADP3804 is placed in low power shutdown. With the exception
of the system current sense amplifier, AMP2, all other circuitry
is turned off. The reference and regulators are pulled to ground
during shutdown and all switching is stopped. During this
state, the supply current is less than 10 µA. Also, the BAT,
CS+, CS-, and SW pins go to high impedance to minimize
current drain from the battery.
REV. PrI
–7–
UVLO
Under-Voltage Lock-Out, UVLO, is included in the ADP3804
to ensure proper start-up. As VCC rises above 1 V, the refer-
ence and regulators will track VCC until they reach their final
voltages. However, the rest of the circuitry is held off by the
UVLO comparator. The UVLO comparator monitors both
regulators to ensure that they are above 5 V before turning on
the main charger circuitry. This occurs when VCC reaches 6 V.
Monitoring the regulator outputs makes sure that the charger
circuitry and driver stage have sufficient voltage to operate
normally. The UVLO comparator includes 300 mV of hyster-
esis to prevent oscillations near the threshold.
Startup Sequence
During a startup from either SD going high or VCC exceeding
the UVLO threshold, the ADP3804 initiates a soft-start se-
quence. The soft-start timing is set by the compensation ca-
pacitor at the COMP pin and an internal 40 µA source.
Initially, both DRVH and DRVL are held low until V
reaches 1 V. This delay time is set by:
For a 1 µF COMP capacitor, t
initial delay, DRVL is turned on first for one period to give the
boost capacitor time to charge up. The duty cycle then ramps
up to its final value with the same ramp rate given for t
For example, if V
ing is started, the duty cycle will be approximately 65%, corre-
sponding to a V
ramp from 0% at V
proximately 25 msec.
Loop Feed Forward
As the startup sequence discussion shows, the response time at
COMP is slowed by the large compensation capacitor. To
speed up the response, two comparators can quickly feed for-
ward around the normal control loop and pull the COMP node
to ground to limit any over shoot in either short circuit or over-
voltage conditions. The over-voltage comparator has a trip
point set to 20% higher than the final battery voltage. The
over-current comparator threshold is set to 200 mV across the
CS pins, which is 25% above the maximum programmable
threshold. When these comparators are tripped, a normal soft-
start sequence is initiated. This will give 0% duty cycle with
DRVH off and DRVL on. The over-voltage comparator is
valuable when the battery is removed during charging. In this
case, the current in the inductor causes the output voltage to
spike up, and the comparator limits the maximum voltage.
Neither of these comparators affect the loop under normal
charging conditions.
t
DELAY
C
COMP
40
COMP
IN
COMP
A
is 16 V and the battery is 10 V when charg-
of ~2 V. The time for the duty cycle to
1
V
= 1 V to 65% at V
DELAY
is 25 msec. After this
COMP
ADP3804
= 2 V is ap-
COMP
(5)
DELAY
.