CMX625D5 CML Microcircuits, CMX625D5 Datasheet - Page 31
CMX625D5
Manufacturer Part Number
CMX625D5
Description
ISDN TA POTS Interface
Manufacturer
CML Microcircuits
Datasheet
1.CMX625D5.pdf
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ISDN TA POTS Interface
Notes:
* t
* t
* t
* FSC
* t
* t
2000 Consumer Microcircuits Limited
Typical UART Timings (See Figures 9a and 9b)
t
t
T
T
T
T
DUDC
DUDF
DCL
DCL
R
FSCS
FSCH
FSK
DLY
DRDY
UFL
/ t
F
IOM-2 Bus Timing (See Figure 13)
*
1. Condition C
DCL clock period in TE Mode
DCL clock period in non-TE Mode
DCL clock rise time / fall time
FSC period
FSC set-up time
FSC hold time
DU delay clock (data out)
DU delay frame (data out)
(delay through the modulator)
(1 bit period)
(¼ bit-period)
(¾ bit-period)
These signals are requirements and are not under control of CMX625.
L
= 150pF.
Figure 13 IOM-2 Bus Timing Diagram
31
Notes
Notes
Min.
Min.
70
40
-
-
-
-
-
-
-
-
-
-
Typ.
Typ.
651
244
125
106
833
208
625
-
-
-
-
-
Max.
100
150
Max.
60
-
-
-
-
-
-
-
-
-
1
1
CMX625
D/625/1
Unit
Unit
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ns
ns
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