HT45R37V Holtek Semiconductor Inc., HT45R37V Datasheet - Page 52

• Manufacturer Part Number: HT45R37V
• Description: C/r-f Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Step 2
Set the SIMEN bit in the SIMCTL0 register to 1 to en-
able the I
Step 3
Set the ESIM and EMFI0 bits of the interrupt control
register to enable the I
Rev. 1.00
Start Signal
The START signal can only be generated by the mas-
ter device connected to the I
microcontroller, which is only a slave device. This
START signal will be detected by all devices con-
nected to the I
that the I
be set. A START condition occurs when a high to low
transition on the SDA line takes place when the SCL
line remains high.
Slave Address
The transmission of a START signal by the master will
be detected by all devices on the I
mine which slave device the master wishes to com-
municate with, the address of the slave device will be
sent out immediately following the START signal. All
slave devices, after receiving this 7-bit address data,
will compare it with their own 7-bit slave address. If the
address sent out by the master matches the internal
address of the microcontroller slave device, then an
internal I
next bit following the address, which is the 8th bit, de-
fines the read/write status and will be saved to the
SRW bit of the SIMCTL1 register. The device will then
transmit an acknowledge bit, which is a low level, as
the 9th bit. The microcontroller slave device will also
set the status flag HAAS when the addresses match.
As an I
when the program enters the interrupt subroutine, the
HAAS bit should be examined to see whether the in-
terrupt source has come from a matching slave ad-
dress or from the completion of a data byte transfer.
When a slave address is matched, the device must be
placed in either the transmit mode and then write data
to the SIMDR register, or in the receive mode where it
must implement a dummy read from the SIMDR regis-
ter to release the SCL line.
SRW Bit
The SRW bit in the SIMCTL1 register defines whether
the microcontroller slave device wishes to read data
from the I
microcontroller should examine this bit to determine if
it is to be a transmitter or a receiver. If the SRW bit is
set to 1 then this indicates that the master wishes to
re a d da t a fro m the I
microcontroller slave device must be setup to send
data to the I
data to the I
device must be setup to read data from the I
a receiver.
0 then this indicates that the master wishes to send
2
2
C bus.
C bus interrupt can come from two sources,
2
2
C bus interrupt signal will be generated. The
C bus is busy and therefore the HBB bit will
2
C bus or write data to the I
2
2
C bus, therefore the microcontroller slave
C bus as a transmitter. If the SRW bit is
2
C bus. When detected, this indicates
2
C bus interrupt.
2
C bus , therefo r e the
2
C bus and not by the
2
C bus. To deter-
2
C bus. The
2
C bus as
52
Acknowledge Bit
After the master has transmitted a calling address,
any slave device on the I
address matches the calling address, must generate
an acknowledge signal. This acknowledge signal will
inform the master that a slave device has accepted its
calling address. If no acknowledge signal is received
by the master then a STOP signal must be transmitted
by the master to end the communication. When the
HAAS bit is high, the addresses have matched and
the microcontroller slave device must check the SRW
bit to determine if it is to be a transmitter or a receiver.
If the SRW bit is high, the microcontroller slave device
should be setup to be a transmitter so the HTX bit in
the SIMCTL1 register should be set to 1 if the SRW
bit is low then the microcontroller slave device should
be setup as a receiver and the HTX bit in the SIMCTL1
register should be set to 0 .
Data Byte
The transmitted data is 8-bits wide and is transmitted
after the slave device has acknowledged receipt of its
slave address. The order of serial bit transmission is
the MSB first and the LSB last. After receipt of 8-bits of
data, the receiver must transmit an acknowledge sig-
nal, level 0 , before it can receive the next data byte.
If the transmitter does not receive an acknowledge bit
signal from the receiver, then it will release the SDA
line and the master will send out a STOP signal to re-
lease control of the I
will be stored in the SIMDR register. If setup as a
transmitter, the microcontroller slave device must first
write the data to be transmitted into the SIMDR regis-
ter. If setup as a receiver, the microcontroller slave de-
vice must read the transmitted data from the SIMDR
register.
Receive Acknowledge Bit
When the receiver wishes to continue to receive the
next data byte, it must generate an acknowledge bit,
known as TXAK, on the 9th clock. The microcontroller
slave device, which is setup as a transmitter will check
the RXAK bit in the SIMCTL1 register to determine if it
is to send another data byte, if not then it will release
the SDA line and await the receipt of a STOP signal
from the master.
Data Timing Diagram
2
C bus. The corresponding data
2
C bus, whose own internal
October 20, 2009
HT45R37V