LMX2364 National Semiconductor Corporation, LMX2364 Datasheet - Page 36

• Manufacturer Part Number: LMX2364
• Description: 2.6 Ghz Pllatinum Fractional Rf Frequency Synthesizer With 850 Mhz Integer If Frequency Synthesizer
• Manufacturer: National Semiconductor Corporation

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Supplemental Information
3.3 DETERMINING THE THEORETICAL LOCK TIME
IMPROVEMENT AND FASTLOCK RESISTOR, R2
The loop bandwidth multiplier, K, is necessary in order to
determine the theoretical impact of FastLock/CSR on the
loop bandwidth and also which resistor should be switched
in parallel with the loop filter resistor R2. K = K_Kphi x
K_Fcomp where K is the loop gain multiplier K_Kphi and
K_Fcomp are the ratio of the FastLock currents and com-
parison frequencies to their steady state conditions. Note
that this should always be greater than or equal to one.
K_Fcomp is the ratio of the FastLock comparison frequency
to the steady state comparison frequency. If this ratio is less
than one, this implies that the CSR is being used.
The change in loop bandwidth is dependent upon the loop
gain multiplier, K. The theoretical improvement in lock time is
given below, but the actual improvement will be less than this
due to the glitch that is caused by disengaging FastLock.
The theoretical improvement is given to show an upper
bound on what improvement is possible with FastLock. In
the case that K
* These modes of operation are generally not recommended
3.4 USING FASTLOCK AND CSR TO AVOID CYCLE
SLIPPING
In the case that the comparison frequency is very large ( ie.
70 x ) of the loop bandwidth, cycle slipping may occur when
an instantaneous phase error is presented to the phase
Loop Gain Multiplier,
<
16:1
1:8*
1:4*
1:2*
1, this implies the CSR is being engaged
K:1
1:1
2:1
4:1
8:1
K
Bandwidth/Steady
FastLock Loop
State Loop
(Continued)
0.35
0.50
0.71
1.00
1.41
2.00
2.83
4.00
36
When K is greater than one, is necessary to switch a Fast-
Lock resistor, R2’, in parallel with R2 in order to keep the
loop filter optimized and maintain the same phase margin.
After the PLL has achieved a frequency that is sufficiently
close to the desired frequency, the resistor R2’ is disengaged
and the charge pump current is and comparison frequency
are returned to normal. Of special concern is the glitch that is
caused when the resistor R2’ is disengaged. This glitch can
take up a significant portion of the lock time. The LMX2364
has enhanced switching circuitry to minimize this glitch and
therefore improve the lock time.
and that the theoretical lock time will be degraded. However,
since this mode reduces or eliminates cycle slipping, the
actual lock time may be better in cases where the loop
bandwidth is small relative to the comparison frequency.
Realize that the theoretical lock time multiplier does not
account for the FastLock/CSR disengagement glitch, which
is most severe for larger values of K.
detector. This can be reduced by increasing the loop band-
width during frequency aquisition, decreasing the compari-
son frequency during frequency acquisition, or some combi-
nation of the these. If increasing the loop bandwidth during
frequency acquisition is not sufficient to reduce cycle slip-
ping, the LMX2364 also has a routine to decrease the com-
parison frequency.
20050640
R2’ Value
R2/0.41
R2/1.83
R2/3.00
open
open
open
open
R2
Theoretical Lock
Time Multiplier
x 2.828
x 2.000
x 1.414
x 1.000
x 0.707
x 0.500
x 0.354
x 0.250
1/