LMX2364 National Semiconductor Corporation, LMX2364 Datasheet - Page 33

• Manufacturer Part Number: LMX2364
• Description: 2.6 Ghz Pllatinum Fractional Rf Frequency Synthesizer With 850 Mhz Integer If Frequency Synthesizer
• Manufacturer: National Semiconductor Corporation

Reg
R6
Programming Description
2.9 R6 REGISTER
2.9.1 MUX[3:0] — Coltrol Word for the Ftest/LD Pin
The MUX[3:0] control word is used to determine the function of the Ftest/LD output pin. The pin can be setup as a general-
purpose CMOS TRI-STATE I/O pin, a digital filtered lock detect pin, an analog lock detect pin (push-pull or open drain output), or
used to view the output of the various R & N dividers.
2.9.2 OSC — Single Resonator Mode
The OSC bit selects whether the oscillator input pins OSCinIF and OSCinRF drive the IF and RF R dividers separately or by a
common input signal path. When OSC is set to 0, the OSCinIF pin drives the IF R divider while the OSCinRF pin drives the RF
R divider. When the OSC bit is set to “1” the OSCinIF pin drives both the RF R and IF R counters. Note that setting the OSC mode
to “1” does not allow the use of a crystal. This part does not include the inverter for use in construction of a crystal oscillator.
2.9.3 PD_M — Power Down Mode
This bit determines if a power down event for either synthesizer will be handled synchronously or asynchronously with respect to
a charge pump event. Synchronous powerdown means that the PLL does not power down until the charge pump turns off.
Asynchronous powerdown means that the PLL powers down, regardless of the charge pump state. When set to one,
synchronous mode is enabled. When set to 0, asynchronous mode is enabled. The setting of this bit applies to both the RF & IF
synthesizers.
2.9.4 FE — Fractional Compensation Enable
For integer mode (RF_OM = 0 ) mode, this bit should always be set to 0. For fractional mode (RF_OM = 1), this bit should be set
to 1 for the best fractional spurs. However, there may be applications using fractional mode where it would be beneficial to set
this bit to 0. Disabling this bit will drastically degrade the fractional spurs, but will also result in a small improvement in phase
noise, which may be practical for some applications.
23
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
22
0
0
21
0
20
FE
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
MUX[3:0]
19
Compensation
0
18
Fractional
Circuitry
Disabled
Enabled
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
17
FE
16
0
(Continued)
15
Default State
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Illegal State
0
Integer
14
Mode
DATA[20:0]
0
13
0
Disabled
General Purpose I/O. Logic HIGH Output
General Purpose I/O. Logic LOW Output
RF & IF Analog Lock Detect (Width of
narrow low pulses determines lock)
RF Analog Lock Detect (Width of narrow
low pulses determines lock)
IF Analog Lock Detect (Width of narrow
low pulses determines lock)
RF & IF Digital Lock Detect (High = Lock)
RF Digital Lock Detect (High = Lock)
IF Digital Lock Detect (High = Lock)
RF & IF Analog Lock Detect (Width of
narrow low pulses determines lock)
RF Analog Lock Detect (Width of narrow
low pulses determines lock)
IF Analog Lock Detect (Width of narrow
low pulses determines lock)
IF R Divider/2 (Output is divided by 2 to
simplify testing)
IF N Divider/2 (Output is divided by 2 to
simplify testing)
RF R Divider/2 (Output is divided by 2 to
simplify testing)
RF N Divider/2 (Output is divided by 2 to
simplify testing)
12
33
0
Ftest/LD Output Pin Function
Approximate Spur
11
Improvement
0
20 dB
10
0 dB
0
9
Fractional Mode
PD_
M
8
OSC
Approximate Phase
7
Degradation
6
Noise
0 dB
7 dB
MUX[3:0]
5
4
High Impedance
Output Type
Open-Drain
Open-Drain
Open-Drain
3
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
Push-Pull
C2
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2
1
C1
1
1
C0
0
0