LMX2364 National Semiconductor Corporation, LMX2364 Datasheet - Page 32

• Manufacturer Part Number: LMX2364
• Description: 2.6 Ghz Pllatinum Fractional Rf Frequency Synthesizer With 850 Mhz Integer If Frequency Synthesizer
• Manufacturer: National Semiconductor Corporation

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Reg
R5
Programming Description
2.8 R5 REGISTER
The R5 Register is used to setup and control the FastLock circuitry for the RF synthesizer.
2.8.1 RF_TOC[13:0] — FastLock Timeout Counter, RF Synthesizer
The RF_TOC[13:0] word controls the operation of the RF FastLock circuitry as well as the function of the FLoutRF output pin.
When RF_TOC is set to a value between 0 and 3, the RF timeout counter is disabled and the FLoutRF pin operates as a general
purpose I/O pin. When RF_TOC is set to a value between 4 and 16383, the RF FastLock mode is enabled and FLoutRF is utilized
as the RF FastLock output pin. The value programmed into RF_TOC represents the number of phase comparison cycles that the
RF synthesizer will spend in the FastLock state.
2.8.2 RF_CPF[1:0] — FastLock Charge Pump Gain, RF Synthesizer
The RF_CPF[1:0] word is used to control the charge pump gain for the RF synthesizer when FastLock is enabled and engaged.
Four different CP gains are supported ranging from 1 to 16 mA. Note that when RF FastLock mode is disengaged or disabled the
charge pump gain is controlled by RF_CP[1:0].
2.8.3 RF_OM[1:0] — RF Synthesizer Operating Mode
RF_OM[1:0] controls the operating mode of the RF synthesizer. The various operating modes are described below:
RF Synthesizer Operating Mode Descriptions
Note that the Fractional Enable Bit, FE (R6[16]) needs to be set appropriately. Enabling the fractional compensation in Integer
mode always degrades performance. It is generally recommended to enable it in fractional mode, although there may be some
rare exceptions that it may be set to 0.
2.8.4 RF_CSR[1:0] — Cycle Slip Reduction Control, RF Synthesizer
RF_CSR[1:0] controls the operation of the cycle slip reduction circuitry. This circuit can be used eliminate the occurrence of phase
detector cycle slips when operating in Fractional Mode (RF_OM = 1). When operating in integer mode,the cycle slip reduction
circuitry should be disabled by setting RF_CSR = 0.
23
0
RF_TOC[13:0]
16,383
RF_OM
CSR[1:0]
22
…
0
1
2
3
4
RF_
0
1
2
3
21
RF_CSR
20
OM[1:0]
0
1
2
3
RF_
RF_CPF[1:0]
FE
19
<
FastLock Mode
R6[16]
0
1
2
3
X
X
0
1
CPF[1:0]
18
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Manual
RF_
>
17
CSR State
Disabled
Enabled
Enabled
Enabled
16
Operating Mode
Fractional
Reserved
Reserved
(Continued)
Integer
15
FastLock Period
14
DATA[20:0]
[CP Events]
16383
13
N/A
N/A
N/A
…
3
4
RF synthesizer always operates as an Integer N PLL
RF synthesizer always operates as a Fractional N PLL
Do Not use this mode
Do Not use this mode.
12
32
11
Sample Rate Reduction Factor
RF_TOC[13:0]
10
Logic LOW State. Force RF Change Pump to 16 mA
Operating Mode Description
9
N/A
1/2
1/4
1/8
Charge Pump Current
8
FLoutRF Pin Functionality
7
16 mA
1 mA
4 mA
8 mA
Logic HIGH State
Logic LOW State
High Impedance
6
FastLock
FastLock
FastLock
5
4
3
C2
2
1
C1
1
0
C0
0
1