LMX2364 National Semiconductor Corporation, LMX2364 Datasheet - Page 3

• Manufacturer Part Number: LMX2364
• Description: 2.6 Ghz Pllatinum Fractional Rf Frequency Synthesizer With 850 Mhz Integer If Frequency Synthesizer
• Manufacturer: National Semiconductor Corporation

TSSOP
Pin Descriptions
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8
9
1
Pin Number
SLE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
VccRF
VcpRF
CPoutRF
GND
FinRF
FinRF*
GND
OSCinRF
OSCinIF
Ftest/LD
ENRF
ENIF
CLK
DATA
LE
GND
FinIF*
FinIF
GND
CPoutIF
VcpIF
VccIF
FLoutIF
FLoutRF
Pin
RF PLL power supply voltage input. Must be equal to V
5.5V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
Power supply for RF charge pump. Must be ≥ V
RF charge pump output.
Ground for RF PLL digital circuitry.
RF prescaler input. Small signal input from the VCO.
RF prescaler complementary input. For single-ended operation, a bypass capacitor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
Ground for RF PLL analog circuitry.
RF R counter input. Has a V
be driven from an external CMOS or TTL logic gate.
Oscillator input which can be configured to drive both the IF and RF R counter inputs
or only the IF R counter depending on the state of the OSC programming bit.
Programmable multiplexed output pin. Can function as general purpose CMOS
TRI-STATE
divider output.
RF PLL Enable. Powers down RF N and R counters, prescaler, and TRI-STATE
charge pump output when LOW, regardless of the state RF_PD bit. Bringing ENRF
high powers up RF PLL depending on the state of RF_PD control bit.
IF PLL Enable. Powers down IF N and R counters, prescaler, and will TRI-STATE the
charge pump output when LOW, regardless of the state IF_PD bit. Bringing ENIF high
powers up IF PLL depending on the state of IF_PD control bit.
High impedance CMOS Clock input. Data for the control registers is clocked into the
24-bit shift register on the rising edge.
Binary serial data input. Data entered MSB first. The last three bits are the control
bits. High impedance CMOS input.
Latch enable. High impedance CMOS input. Data stored in the shift register is loaded
into one of the 7 internal latches when LE goes HIGH.
Ground for IF analog circuitry.
IF prescaler complementary input. For single-ended operation, a bypass capacitor
should be placed as close as possible to this pin and be connected directly to the
ground.
IF prescaler input. Small signal input from the VCO.
Ground for IF digital circuitry.
IF charge pump output.
Power supply for IF charge pump. Must be ≥ V
IF power supply voltage input. Must be equal to V
5.5V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
IF FastLock Output. Also functions as Programmable TRI-STATE CMOS output.
RF FastLock Output. Also functions as Programmable TRI-STATE CMOS output.
®
I/O, analog lock detect output, digital filtered lock detect output, or N & R
3
CC
/2 input threshold when configured as an input and can
Description
VccRF
VccRF
VccRF
and V
and V
. Input may range from 2.7V to
VccIF
VccIF
VccIF
. May range from 2.7V to
.
.
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