STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 23
STG3005A2S
Manufacturer Part Number
STG3005A2S
Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Manufacturer
STMicroelectronics
Datasheet
1.STG3005A2S.pdf
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128-BIT 3D MULTIMEDIA ACCELERATOR
5
5.1
The RIVA128ZX supports a glueless interface to PCI 2.1 with both master and slave capabilities. The host
interface is fully compliant with the 32-bit PCI 2.1 specification.
The Multimedia Accelerator supports PCI bus operation up to 33MHz with zero-wait state capability and
full bus mastering capability handling burst reads and burst writes.
Figure 16. PCI interface pin connections
Table 5. PCI bus commands supported by the RIVA128ZX
Bus master
Memory read and write
Memory read line
Memory read multiple
PCI 2.1 LOCAL BUS INTERFACE
RIVA128ZX PCI INTERFACE
PCICBE[3:0]#
PCIDEVSEL#
PCIAD[31:0]
PCIFRAME#
PCITRDY#
PCISTOP#
PCIIRDY#
PCIIDSEL
PCIINTA#
PCIREQ#
PCIGNT#
PCIRST#
PCIPAR
PCICLK
32
4
Bus slave
Memory read and write
I/O read and write
Configuration read and write
Memory read line
Memory read multiple
Memory write invalidate
RIVA128ZX
RIVA128ZX
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