STG3005A2S STMicroelectronics, STG3005A2S Datasheet
STG3005A2S
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STG3005A2S Summary of contents
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KEY FEATURES Fast 32-bit VGA/SVGA High performance 128-bit 2D/GUI/DirectDraw Acceleration Interactive, Photorealistic Direct3D Accelera- tion with advanced effects Pinout backwards compatible with RIVA 128 Massive 1.6Gbytes/s, 100MHz 128-bit wide 8MByte SGRAM framebuffer interface Adds 16Mbit SDRAM support for cost sensitive ...
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RIVA128ZX 1 RIVA128ZX 300PBGA DEVICE PINOUT....................................................................................... 2 PIN DESCRIPTIONS ...................................................................................................................... 2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE ..................................................... 2.2 PCI 2.1 LOCAL BUS INTERFACE ........................................................................................ 2.3 FRAMEBUFFER INTERFACE .............................................................................................. 2.4 VIDEO PORT......................................................................................................................... 2.5 DEVICE ENABLE SIGNALS .................................................................................................. 2.6 DISPLAY INTERFACE .......................................................................................................... ...
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MULTIMEDIA ACCELERATOR 10 POWER-ON RESET CONFIGURATION........................................................................................ 11 DISPLAY INTERFACE ................................................................................................................... 11.1 PALETTE-DAC ...................................................................................................................... 11.2 PIXEL MODES SUPPORTED ............................................................................................... 11.3 HARDWARE CURSOR ......................................................................................................... 11.4 SERIAL INTERFACE............................................................................................................. 11.5 ANALOG INTERFACE .......................................................................................................... 11.6 TV OUTPUT SUPPORT ........................................................................................................ 12 IN-CIRCUIT BOARD TESTING ...
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RIVA128ZX 1 RIVA128ZX 300PBGA DEVICE PINOUT NOTES 1 NIC = No Internal Connection. Do not connect to these pins. 2 VDD=3.3V Signals denoted with an asterisk are defined for future expansion. See Pin Descriptions , Section 2, page 5 for ...
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MULTIMEDIA ACCELERATOR 2 PIN DESCRIPTIONS 2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE Signal I/O Description AGPST[2:0] I AGP status bus providing information from the arbiter to the RIVA128ZX on what it may do. AGPST[2:0] only have meaning to the ...
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RIVA128ZX Signal I/O Description PCICBE[3:0]# I/O Multiplexed bus command and byte enable signals. During the address phase of a trans- action PCICBE[3:0]# define the b us command, during the data phase PCICBE[3:0]# are used as byte enables. The byte enables ...
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MULTIMEDIA ACCELERATOR Signal I/O Description PCIGNT# I Grant. This signal indicates to the RIVA128ZX that access to the bus has been granted and it can now become bus master. When connected to AGP additional information is provided on ...
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RIVA128ZX 2.5 DEVICE ENABLE SIGNALS Signal I/O Description ROMCS# O Enables reads from an external 64Kx 8 or 32Kx8 ROM or Flash ROM. This signal is used in conjunction with framebuffer data lines as described above in Section 2.3. 2.6 ...
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MULTIMEDIA ACCELERATOR 2.9 TEST Signal I/O Description TESTMODE I For designs which will be tested in-circuit, this pin should be connected to GND through a 10K pull-down resistor, otherwise this pin should be connected directly to GND. When ...
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RIVA128ZX 3 OVERVIEW OF THE RIVA128ZX The RIVA128ZX is the first 128-bit 3D Multimedia Accelerator to offer unparalleled 2D and 3D per- formance, meeting all the requirements of the mainstream PC graphics market and Microsoft’s PC’97. The RIVA128ZX introduces the ...
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MULTIMEDIA ACCELERATOR Fully supports the “Execute” model on both PCI and AGP 3.3 2D ACCELERATION The RIVA128ZX’s 2D rendering engine delivers industry-leading Windows acceleration perfor- mance: 100MHz 128-bit graphics engine optimized for single cycle operation into the 128-bit ...
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RIVA128ZX Support for scaled field interframing for reduced motion artifacts and reduced storage Per-pixel color keying Multiple video windows with hardware color space conversion and filtering Planar YUV12 (4:2:0) to/from packed (4:2:2) conversion for software MPEG acceleration and H.261 video ...
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MULTIMEDIA ACCELERATOR 3.10 CUSTOMER EVALUATION KIT A Customer Evaluation Kit (CEK) is available for evaluating the RIVA128ZX. The CEK includes a PCI or AGP adapter card designed to support the RIVA128ZX feature set, an evaluation CD-ROM containing a ...
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RIVA128ZX 4 ACCELERATED GRAPHICS PORT (AGP) INTERFACE The Accelerated Graphics Port (AGP high performance, component level interconnect targeted at 3D graphical display applications and based on performance enhancements to the PCI local bus. Figure 1. System block diagram ...
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MULTIMEDIA ACCELERATOR the AGP bridge chip and RIVA128ZX are the only devices on the AGP bus - all other I/O devices re- main on the PCI bus. The add-in slot defined for AGP uses a new con- nector ...
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RIVA128ZX Figure 3. Basic PCI transaction on AGP 1 2 PCICLK PCIFRAME# PCIAD[31:0] PCICBE[3:0]# PCIIRDY# PCITRDY# PCIDEVSEL# PCIREQ# PCIGNT# xxx 111 AGPST[2:0] An example of a PCI transaction occurring between an AGP command cycle and return of data is shown ...
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MULTIMEDIA ACCELERATOR Figure 5. Basic AGP pipeline concept Bus Idle Pipelined data transfer Intervene A1 A2 cycles Pipelined AGP requests Pipeline operation Memory access pipelining provides the main per- formance enhancement of AGP over PCI. AGP pipelined bus ...
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RIVA128ZX Figure 6. Single address - no delay by master 1 2 PCICLK AGPPIPE# PCIAD[31:0] PCICBE[3:0]# PCIREQ# PCIGNT# xxx 111 AGPST[2:0] Figure 7 shows the RIVA128ZX enqueuing 4 requests, where the first request is delayed by the maximum 2 cycles ...
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MULTIMEDIA ACCELERATOR Figure 8. 2X Read data, no delay 1 PCICLK PCIAD[31:0] AGPADSTBx AGPRBF# PCITRDY# PCIREQ# PCIGNT# xxx AGPST[2:0] Figure 8 shows 32 bytes being transferred during 4 clocks (compared with 16 bytes in AGP 1x mode). The ...
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RIVA128ZX Figure 10. 2X Basic write no delay 1 2 PCICLK PCIAD[31:0] PCICBE# AGPADSTBx PCIIRDY# PCITRDY# PCIREQ# PCIGNT# AGPST[2:0] xx xxx Figure basic write transaction that transfers data at the 2X rate. There is no difference in ...
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MULTIMEDIA ACCELERATOR AGP timing specification Figure 12. AGP clock specification 0.6VDD 0.5VDD PCICLK 0.4VDD 0.3VDD Table 1. AGP clock timing parameters Symbol Parameter t PCICLK period CYC t PCICLK high time HIGH t PCICLK low time LOW PCICLK ...
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RIVA128ZX Figure 14. AGP timing diagram (2X data transfer mode) AGPCLK Output data t TSF Output strobe Input data Input strobe Table 3. AGP timing parameters (2X data transfer mode) Symbol Parameter t AGPCLK to transmit strobe falling edge TSF ...
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MULTIMEDIA ACCELERATOR 5 PCI 2.1 LOCAL BUS INTERFACE 5.1 RIVA128ZX PCI INTERFACE The RIVA128ZX supports a glueless interface to PCI 2.1 with both master and slave capabilities. The host interface is fully compliant with the 32-bit PCI 2.1 ...
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RIVA128ZX 5.2 PCI TIMING SPECIFICATION The timing specification of the PCI interface takes the form of generic setup, hold and delay times of tran- sitions to and from the rising edge of PCICLK as shown in Figure 17. Figure 17. ...
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MULTIMEDIA ACCELERATOR Figure 18. PCI Target write - Slave Writ PCICLK PCIAD[31:0] address PCICBE[3:0]# bus cmd PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# Figure 19. PCI Target write - Slave Write (multiple 32-bit with zero wait state DEVSEL# response) PCICLK PCIAD[31:0] ...
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RIVA128ZX Figure 20. PCI Target read - Slave Read (1-cycle single word read) PCICLK PCIAD[31:0] address PCICBE[3:0]# bus cmd PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# Figure 21. PCI Target read - Slave Read (slow single word read) PCICLK PCIAD[31:0] address PCICBE[3:0]# bus ...
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MULTIMEDIA ACCELERATOR Figure 22. PCI Master write - multiple word PCICLK PCIREQ# PCIGNT# PCIAD[31:0] address PCICBE[3:0]# bus cmd PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# Figure 23. PCI Master read - multiple word PCICLK PCIREQ# PCIGNT# PCIAD[31:0] address PCICBE[3:0]# bus cmd ...
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RIVA128ZX Figure 24. PCI Target configuration cycle - Slave Configuration Write PCICLK AD[31:0] address PCICBE[3:0]# bus cmd PCIFRAME# PCIIDSEL PCIIRDY# PCITRDY# PCIDEVSEL# Figure 25. PCI Target configuration cycle - Slave Configuration Read PCICLK PCIAD[31:0] address PCICBE[3:0]# bus cmd PCIFRAME# PCIIDSEL ...
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MULTIMEDIA ACCELERATOR Figure 26. PCI basic arbitration cycle PCICLK PCIREQ#_a PCIREQ#_b PCIGNT#_a PCIGNT#_b PCIFRAME# PCIAD[31:0] Figure 27. Target initiated termination PCICLK 1 PCIFRAME# PCIIRDY# PCITRDY# PCISTOP# PCIDEVSEL# PCICLK 1 2 PCIFRAME# PCIIRDY# PCITRDY# PCIPCISTOP# PCIDEVSEL# Disconnect - C ...
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RIVA128ZX 6 FRAMEBUFFER INTERFACE The RIVA128ZX framebuffer interface supports SDRAM and SGRAM memory. Using SDRAM it can be configured with an 8MByte 64-bit data bus. With SGRAM it can be configured with 4MByte 64-bit data bus or ...
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MULTIMEDIA ACCELERATOR 6.1 SDRAM INTERFACE Two extra address lines are required to support 8MByte SDRAM compared with those needed for 4MByte SGRAM on RIVA 128. These are the A10 signal which was defined on the RIVA 128 pinout ...
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RIVA128ZX 6.2 SGRAM INTERFACE Signal changes between RIVA 128 and RIVA128ZX The extra address signal (FBA[10]) required to address 16Mbit SGRAM devices was defined on RIVA 128 and was connected to pin 30 of the SGRAM in the RIVA 128 ...
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MULTIMEDIA ACCELERATOR Figure 30. 4 MByte SGRAM configurations using 16Mbit devices FBDQM[0]# FBDQM[1]# Bank 0 FBDQM[2]# 512K 32 FBDQM[3]# SGRAM FBCS[0]# FBCLK0 FBD[127:0] FBDQM[0]# FBDQM[1]# Bank 0 FBDQM[2]# 512K 32 FBDQM[3]# SGRAM FBCS[0]# FBCLK0 FBD[127:0] NOTE 1 The ...
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RIVA128ZX Figure 31. 8MByte SGRAM configuration using 16Mbit devices FBDQM[0]# FBDQM[1]# Bank 0 FBDQM[2]# 512K 32 FBDQM[3]# SGRAM FBCS[0]# FBCLK0 FBDQM[4]# FBDQM[5]# Bank 1 FBDQM[6]# 512K 32 FBDQM[7]# SGRAM FBCS[0]# FBCLK1 FBD[127:0] 34/85 128-BIT 3D MULTIMEDIA ACCELERATOR FBDQM[8]# FBDQM[9]# FBD[31:0] ...
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MULTIMEDIA ACCELERATOR 6.3 SDRAM/SGRAM ACCESSES AND COMMANDS Read and write accesses to SDRAM/SGRAM are burst oriented. SDRAM/SGRAM commands supported by the RIVA128ZX are shown in Table 9. Initialization of the memory devices is performed in the standard SDRAM/SGRAM ...
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RIVA128ZX Table 9. Truth table of supported SGRAM commands 1 Command FBCS0#, FBCS1# Command inhibit (NOP operation (NOP) L Active (select bank and L activate row) Read (select bank and L column and start read burst) Write (select ...
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MULTIMEDIA ACCELERATOR 6.4 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of memory to give reduced clock skew and loading. Additionally there is a clock feedback loop between FBCLK2 and ...
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RIVA128ZX Symbol Parameter t Write data hold time DH t Read data hold time OH t Read data access time AC t Data out low impedance time LZ Figure 34. SDRAM/SGRAM random read accesses within a page, read latency of ...
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MULTIMEDIA ACCELERATOR Table 11. SDRAM/SGRAM I/O timing parameters Symbol Parameter t Data out high impedance time HZ t Write data setup time DS Figure 37. SDRAM/SGRAM random write cycles within a page FBCLKx Command write FBA[10:0] bank, col ...
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RIVA128ZX Figure 40. SDRAM/SGRAM read to precharge, read latency of three FBCLKx Command FBA[10:0] FBD[63:0] NOTE 1 FBDQM is active (low) Figure 41. SDRAM/SGRAM Write to Precharge FBCLKx FBDQM# Command write nop FBA[10:0] bank, col n FBD[63:0] write data n ...
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MULTIMEDIA ACCELERATOR Symbol Parameter t Refresh period (1024 cycles) REF t Precharge command period RP t Active bank A to Active bank B command RRD period t Transition time T t Write recovery time WR RIVA128ZX Min. Max. ...
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RIVA128ZX 7 VIDEO PLAYBACK ARCHITECTURE The RIVA128ZX video playback architecture is designed to allow playback of CCIR PAL or NTSC video formats with the highest quality while requir- ing the smallest video surface. The implementa- tion is optimized around the ...
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MULTIMEDIA ACCELERATOR 7.1 VIDEO SCALER PIPELINE The RIVA128ZX video scaler pipeline performs stretching of video images in any arbitrary factor in both horizontal and vertical directions. The video scaler pipeline consists of the following stages: 1 Vertical stretching ...
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RIVA128ZX Figure 44. Displaying 2 fields with 1:1 ratio Frame 1 (Top field) Line 11 Interpolated line (Line 11 & 13) Line 13 The RIVA128ZX video overlay handles interlaced video by displaying every field, at the original frame rate of ...
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MULTIMEDIA ACCELERATOR 8 VIDEO PORT The RIVA128ZX Multimedia Accelerator introduc multi-function Video Port that has been de- signed to exploit the bus mastering functionality of the RIVA128ZX. The Video Port is compliant with a simplified ITU-R-656 ...
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RIVA128ZX 8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC The Media Port transfers data using a Polling Pro- tocol. The Media Port is enabled on the RIVA128ZX by the host system software. The first cycle after being enabled is a ...
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MULTIMEDIA ACCELERATOR 8.3 TIMING DIAGRAMS Figure 46. Poll cycle MPCLK MPFRAME# ] MP_AD[7:0 A0 MPDTACK# Figure 47. Poll cycle throttled by slave MPCLK MPFRAME# ] MP_AD[7:0 A0 MPDTACK# Figure 48. CPU write cycle MPCLK MPFRAME# ] MP_AD[7:0 A0 ...
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RIVA128ZX Figure 50. CPU read issue cycle - cannot be throttled by slave MPCLK MPFRAME# ] MP_AD[7:0 A0 Figure 51. CPU read_receive cycle MPCLK MPFRAME# ] MP_AD[7:0 A0 MPDTACK# Figure 52. CPU read_receive cycle - throttled by slave MPCLK MPFRAME# ...
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MULTIMEDIA ACCELERATOR Figure 54. CD write cycle - terminated by slave in middle of transfer MPCLK MPFRAME# MP_AD[7:0] A0 MPDTACK# MPSTOP# Figure 55. CD write cycle - terminated by slave on byte 31 MPCLK MPFRAME# MP_AD[7:0] A0 MPDTACK# ...
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RIVA128ZX Figure 58. UCD read cycle, terminated by slave, throttled by slave MPCLK MPFRAME# MP_AD[7:0] A0 MPDTACK# MPSTOP# Figure 59. UCD read cycle, slave termination after MPFRAME# deasserted, data taken MPCLK MPFRAME# MP_AD[7:0] A0 MPDTACK# MPSTOP# Figure 60. UCD read ...
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MULTIMEDIA ACCELERATOR 8.4 656 MASTER MODE Table 15 shows the Video Port pin definition when the RIVA128ZX is configured in ITU-R-656 Master Mode. Before entering this mode, RIVA128ZX dis- ables all Video Port devices so that the bus ...
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RIVA128ZX 8.5 VBI HANDLING IN THE VIDEO PORT RIVA128ZX supports two basic modes for VBI data capture. VBI mode 1 is for use with the Philips SAA7111A digitizer, VBI mode 2 is for use with the Samsung KS0127 digitizer. In ...
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MULTIMEDIA ACCELERATOR 9 BOOT ROM INTERFACE BIOS and initialization code for the RIVA128ZX is accessed from a 32KByte ROM. The RIVA128ZX mem- ory bus interface signals FBD[15:0] and FBD[31:24] are used to address and access one of 64KBytes ...
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RIVA128ZX Table 18. ROM interface timing parameters Symbol Parameter t ROMCS# active pulse width BRCS t ROMCS# precharge time BRCA t Read valid to ROMCS# active BRV t Read hold from ROMCS# inactive BRH t Address setup to ROMCS# active ...
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MULTIMEDIA ACCELERATOR 10 POWER-ON RESET CONFIGURATION The RIVA128ZX latches its configuration on the trailing edge of RST# and holds its system bus in- terface in a high impedance state until this time. To accomplish this, pull-up or pull-down ...
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RIVA128ZX [2] RAM Type 0 = 16Mbit internal bank SGRAM or 16Mbit SDRAM. The BIOS should test the memory to determine whether it supports internal banks 8Mbit, 2 internal bank SGRAM. Although ...
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MULTIMEDIA ACCELERATOR 11 DISPLAY INTERFACE 11.1 PALETTE-DAC The Palette-DAC integrated into the RIVA128ZX supports a traditional pixel pipeline with the follow- ing enhancements: Support for 10:10:10, 8:8:8, 5:6:5 and 5:5:5 di- rect color pixel modes Support for dynamic ...
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RIVA128ZX mode pixel format, the least significant bits of each color are located separately in the top byte of the pixel. This also permits an 8:8:8 mode without gamma with <1% error if desired ...
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MULTIMEDIA ACCELERATOR 11.4 SERIAL INTERFACE The RIVA128ZX serial interface supports connec- tion to DDC1/2B, DDC2AB and DDC2B+ compli- ant monitors and to serial interface controlled vid- eo decoders and tuners. Supported video decoder chips include Philips SAA7110, SAA7111A, ...
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RIVA128ZX 11.5 ANALOG INTERFACE Figure 66. Recommended circuit (crystal circuit is for designs not supporting TV out) VDD Local PLLVDD plane These components should be placed as close to the RIVA128ZX outputs ...
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MULTIMEDIA ACCELERATOR 11.6 TV OUTPUT SUPPORT Reference clock options The RIVA128ZX supports two synthesizer refer- ence clock frequencies; 13.5MHz 14.31818MHz. The reference clock frequency is determined by a crystal or reference clock con- nected to the XTALIN and ...
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RIVA128ZX Figure 68. Interface to monitor or television TV RGB Encoder R RIVA128ZX Monitor detection Figure 68 shows the typical connection of a televi- sion or computer monitor to the RIVA128ZXs’ DAC outputs. The RIVA128ZX ...
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MULTIMEDIA ACCELERATOR 12 IN-CIRCUIT BOARD TESTING The RIVA128ZX has a number of features designed to support in-circuit board testing. These include: Dedicated test mode input and dual-function test mode select pins selecting the following modes: - Pin float ...
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RIVA128ZX 13 ELECTRICAL SPECIFICATIONS 13.1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDD/AVDD DC supply voltage Voltage on input and output pins TS Storage temperature (ambient) TA Temperature under bias Analog output current (per output) DC digital output current (per output) NOTES ...
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MULTIMEDIA ACCELERATOR Symbol Parameter VIL Input logic 0 voltage VOH Output logic 1 level VOL Output logic 0 level IOH Output load current, logic 1 level IOL Output load current, logic 0 level NOTE 1 Tested but not ...
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RIVA128ZX NOTES 1 Blanking pedestals are not supported in TV output mode. 2 VREF = 1.235V, RSET = 147 3 LSB = 1 LSB of 8-bit resolution DAC 8 4 About the midpoint of the distribution of the three DACs ...
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MULTIMEDIA ACCELERATOR 14 PACKAGE DIMENSION SPECIFICATION 14.1 300 PIN BALL GRID ARRAY PACKAGE Figure 69. RIVA128ZX 300 Plastic Ball Grid Array Package dimension reference D2 Pin 1 indicator 0.300 0.100 S SOLDER BALL ...
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... AD722 PAL/NTSC TV Encoder Datasheet , Analog Devices Inc., 1995 8 MK2715 NTSC/PAL Clock Source Datasheet , MicroClock Inc., March 1997 16 ORDERING INFORMATION Device RIVA128ZX 300 pin PBGA RIVA128ZX 300 pin PBGA 68/85 128-BIT 3D MULTIMEDIA ACCELERATOR Package Supply format Trays Tape and reel Part number STG3005A2S STG3005A2S/TR ...
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... APCI Supported bit = 0 = 0x0019 if the power-on reset configuration APCI Supported bit = 1 Vendor Identification Register (0x01 - 0x00) Bits Function 15:0 VENDOR_ID bits allocated by the PCI Special Interest Group to uniquely identify the manufacturer of the device. NVIDIA/STMicroelectronics Vendor ID = 0x12D2 (4818) 0x02 0x01 RIVA128ZX 0x00 ...
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RIVA128ZX Byte offsets 0x07 - 0x04 0x07 Device Status Register (0x07 - 0x06) Bits Function 31 Reserved ...
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MULTIMEDIA ACCELERATOR Command Register (0x05 - 0x04) Bits Function 15:9 Reserved 8 SERR_ENABLE is an enable bit for the SERR# driver. 0=Disables the SERR# driver 1=Enables the SERR# driver 7:6 Reserved 5 PALETTE_SNOOP indicates that VGA compatible devices ...
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RIVA128ZX Byte offsets 0x0B - 0x08 0x0B Class Code Register (0x0B - 0x09) Bits Function 31:8 The ...
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MULTIMEDIA ACCELERATOR Byte offsets 0x0F - 0x0C 0x0F Bits Function 31:24 Reserved 23:16 HEADER_TYPE identifies ...
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RIVA128ZX Byte offsets 0x13 - 0x10 0x13 Base Memory Address Register (0x13 - 0x10) Bits Function 31:24 ...
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MULTIMEDIA ACCELERATOR Byte offsets 0x17 - 0x14 0x17 Base Memory Address Register (0x17 - 0x14) ...
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RIVA128ZX Byte offsets 0x2F - 0x2C 0x2F Subsystem Vendor ID (0x2F - 0x2C) Bits Function 31:16 SUBSYSTEM_ID ...
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MULTIMEDIA ACCELERATOR Byte offsets 0x33 - 0x30 0x33 Expansion ROM Base Address Register (0x33 - ...
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RIVA128ZX Byte offsets 0x37 - 0x34 0x37 Capabilities Pointer Register (0x37 - 0x34) Bits Function 31:8 Reserved ...
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MULTIMEDIA ACCELERATOR Byte offset 0x3F - 0x3C 0x3F MAX_LAT Register (0x3F ) Bits Function 31:24 ...
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RIVA128ZX Byte offsets 0x43 - 0x40 0x43 Writeable Subsystem Vendor ID (0x43 - 0x40) Bits Function 31:16 ...
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MULTIMEDIA ACCELERATOR Byte offsets 0x4B - 0x48 0x4B AGP Status Register (0x4B - 0x48 = ...
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RIVA128ZX Byte offsets 0x4F - 0x4C 0x4F AGP Command Register (0x4F - 0x4C = CAP_PTR + 8) ...
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MULTIMEDIA ACCELERATOR Byte offsets 0x63 - 0x60 0x63 Power Management Capabilities Register (0x63 - 0x60) ...
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RIVA128ZX Byte offsets 0x67 - 0x64 0x67 Power Management Control/Status Register (0x67 - 0x64) Bits Function 31:2 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...