DS2431 Maxim, DS2431 Datasheet - Page 8

• Manufacturer Part Number: DS2431
• Description: The DS2431 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each
• Manufacturer: Maxim

1024-Bit, 1-Wire EEPROM
Contact the factory to set up and register a custom
manufacturer ID. The last row is reserved for future
use. It is undefined in terms of R/W functionality and
should not be used.
In addition to the main EEPROM array, an 8-byte
volatile scratchpad is included. Writes to the EEPROM
array are a two-step process. First, data is written to the
scratchpad and then copied into the main array. This
allows the user to first verify the data written to the
scratchpad prior to copying into the main array. The
device only supports full row (8-byte) copy operations.
For data in the scratchpad to be valid for a copy opera-
tion, the address supplied with a Write Scratchpad
command must start on a row boundary, and 8 full
bytes must be written into the scratchpad.
The protection control registers determine how incom-
ing data on a Write Scratchpad command is loaded
into the scratchpad. A protection setting of 55h (write
protect) causes the incoming data to be ignored and
the target address main memory data to be loaded into
the scratchpad. A protection setting of AAh (EPROM
mode) causes the logical AND of incoming data and
target address main memory data to be loaded into the
scratchpad. Any other protection control register set-
ting leaves the associated memory page open for unre-
stricted write access. Note: For the EPROM mode to
function, the entire affected memory page must first be
programmed to FFh. Protection-control byte settings of
55h or AAh also write protect the protection-control
byte. The protection-control byte setting of 55h does
not block the copy. This allows write-protected data to
be refreshed (i.e., reprogrammed with the current data)
in the device.
Figure 6. Address Registers
8
_______________________________________________________________________________________
TARGET ADDRESS (TA1)
TARGET ADDRESS (TA2)
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
BIT #
T15
AA
T7
7
T14
T6
6
0
T13
T5
PF
5
The copy-protection byte is used for a higher level of
security and should only be used after all other protec-
tion control bytes, user bytes, and write-protected
pages are set to their final value. If the copy-protection
byte is set to 55h or AAh, all copy attempts to the regis-
ter row and user-byte row are blocked. In addition, all
copy attempts to write-protected main memory pages
(i.e., refresh) are blocked.
The DS2431 employs three address registers: TA1,
TA2, and E/S (Figure 6). These registers are common to
many other 1-Wire devices but operate slightly differ-
ently with the DS2431. Registers TA1 and TA2 must be
loaded with the target address to which the data is writ-
ten or from which data is read. Register E/S is a read-
only transfer-status register used to verify data integrity
with write commands. E/S bits E[2:0] are loaded with
the incoming T[2:0] on a Write Scratchpad command
and increment on each subsequent data byte. This is,
in effect, a byte-ending offset counter within the 8-byte
scratchpad. Bit 5 of the E/S register, called PF, is a
logic 1 if the data in the scratchpad is not valid due to a
loss of power or if the master sends fewer bytes than
needed to reach the end of the scratchpad. For a valid
write to the scratchpad, T[2:0] must be 0 and the mas-
ter must have sent 8 data bytes. Bits 3, 4, and 6 have
no function; they always read 0. The highest valued bit
of the E/S register, called authorization accepted (AA),
acts as a flag to indicate that the data stored in the
scratchpad has already been copied to the target
memory address. Writing data to the scratchpad clears
this flag.
T12
T4
4
0
Address Registers and Transfer Status
T11
T3
3
0
T10
T2
E2
2
T1
T9
E1
1
T0
T8
E0
0