ST72321J7-Auto STMicroelectronics, ST72321J7-Auto Datasheet - Page 115
ST72321J7-Auto
Manufacturer Part Number
ST72321J7-Auto
Description
8-bit MCU for automotive with 48 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
Manufacturer
STMicroelectronics
Datasheet
1.ST72321R9-AUTO.pdf
(243 pages)
Specifications of ST72321J7-Auto
Hdflash Endurance
100 cycles, data retention 20 years
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
4 Power Saving Modes
Halt, Active Halt, Wait and Slow
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ST72321xx-Auto
13.7.3
Table 60.
Table 61.
1. If the external clock pin is not available, programming the external clock configuration stops the counter.
Control/status register (CSR)
CSR
3:2 CC[1:0]
Bit
5
4
1
0
ICF1
RO
7
External clock (where available)
EXEDG
IEDG2
Name
PWM
OPM
CR2 register description (continued)
Timer clock selection
One Pulse Mode
Pulse Width Modulation
Clock Control
Input Edge 2
OCF1
External Clock Edge
Timer clock
RO
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the
generated pulse depends on the contents of the OC1R register.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
length of the pulse depends on the value of OC1R register; the period depends on
the value of OC2R register.
The timer clock mode depends on these bits (see
This bit determines which type of level transition on the ICAP2 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
This bit determines which type of level transition on the external clock pin EXTCLK
will trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
6
f
f
f
CPU
CPU
CPU
/ 4
/ 2
/ 8
TOF
RO
5
Doc ID 13829 Rev 1
(1)
ICF2
RO
4
Function
OCF2
RO
3
CC1
0
0
1
1
TIMD
Table
RW
2
Reset value: xxxx x0xx (xxh)
61).
1
Reserved
CC0
0
1
0
1
16-bit timer
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