ST7232AK2 STMicroelectronics, ST7232AK2 Datasheet - Page 26
ST7232AK2
Manufacturer Part Number
ST7232AK2
Description
8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST7232AK1.pdf
(157 pages)
Specifications of ST7232AK2
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, PWM and pulse generator modes
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ST7232A
RESET SEQUENCE MANAGER (Cont’d)
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
6.3.3 External Power-On RESET
To start up the microcontroller correctly, the user
must ensure by means of an external reset circuit
that the reset signal is held low until V
the minimum level specified for the selected f
frequency.
Figure 14. RESET Sequences
26/157
1
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
RUN
t
h(RSTL)in
DD
WATCHDOG UNDERFLOW
is over
ACTIVE
PHASE
EXTERNAL
OSC
RESET
A proper reset signal for a slow rising V
can generally be provided by an external RC net-
work connected to the RESET pin.
6.3.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
RUN
ACTIVE
PHASE
WATCHDOG
RESET
t
w(RSTL)out
w(RSTL)out
RUN
CPU
)
.
Figure
DD
supply
14.
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