ST7232AK2 STMicroelectronics, ST7232AK2 Datasheet - Page 136
ST7232AK2
Manufacturer Part Number
ST7232AK2
Description
8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST7232AK1.pdf
(157 pages)
Specifications of ST7232AK2
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, PWM and pulse generator modes
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ST7232A
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 77. SPI Slave Timing Diagram with CPHA=1
Figure 78. SPI Master Timing Diagram
Notes:
1. Measurement points are done at CMOS levels: 0.3xV
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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1
MISO
MOSI
MISO
MOSI
SS
CPHA=1
CPOL=0
CPHA=1
CPOL=1
OUTPUT
INPUT
SS
INPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
INPUT
OUTPUT
INPUT
see
note 2
see note 2
t
a(SO)
t
su(SS)
HZ
t
t
t
v(MO)
w(SCKH)
w(SCKL)
t
su(MI)
t
su(SI)
MSB OUT
MSB IN
MSB OUT
t
h(MO)
t
MSB IN
h(MI)
1)
t
h(SI)
t
c(SCK)
t
c(SCK)
t
t
t
v(SO)
w(SCKH)
w(SCKL)
DD
and 0.7xV
BIT6 OUT
1)
BIT6 OUT
BIT6 IN
DD
.
BIT1 IN
t
h(SO)
t
t
t
t
r(SCK)
f(SCK)
r(SCK)
f(SCK)
LSB OUT
LSB IN
LSB OUT
LSB IN
t
h(SS)
t
see note 2
dis(SO)
note 2
see
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