LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet - Page 44
LPC1850FET256
Manufacturer Part Number
LPC1850FET256
Description
The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1810FBD144.pdf
(157 pages)
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Table 3.
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See
LPC1850_30_20_10
Preliminary data sheet
Symbol
PC_3
PC_4
PC_5
Pin description
F5
F4
G4
-
-
-
…continued
-
-
-
11
16
20
All information provided in this document is subject to legal disclaimers.
-
-
-
Rev. 3.1 — 15 December 2011
-
-
-
[6]
[3]
[3]
I; PU I/O USB1_ULPI_D5 — ULPI link bidirectional data
I; PU -
I; PU -
-
O
O
I/O GPIO6[2] — General purpose digital input/output pin.
-
-
O
I
I/O USB1_ULPI_D4 — ULPI link bidirectional data
-
I/O GPIO6[3] — General purpose digital input/output pin.
-
I
I/O SD_DAT0 — SD/MMC data bus line 0.
I/O USB1_ULPI_D3 — ULPI link bidirectional data
-
O
I/O GPIO6[4] — General purpose digital input/output pin.
-
I
I/O SD_DAT1 — SD/MMC data bus line 1.
Description
line 5.
R — Function reserved.
U1_RTS — Request to Send output for UART1. Can
also be configured to be an RS-485/EIA-485 output
enable signal for UART1.
ENET_TXD3 — Ethernet transmit data 3 (MII
interface).
R — Function reserved.
R — Function reserved.
SD_VOLT1 — SD/MMC bus voltage select output 1.
ADC1_0 — ADC1, input channel 0.
R — Function reserved.
line 4.
R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).
R — Function reserved.
T3_CAP1 — Capture input 1 of timer 3.
R — Function reserved.
line 3.
R — Function reserved.
ENET_TX_ER — Ethernet Transmit Error (MII
interface).
R — Function reserved.
T3_CAP2 — Capture input 2 of timer 3.
Table
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
2.
© NXP B.V. 2011. All rights reserved.
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