ADCMP567BCPZ Analog Devices Inc, ADCMP567BCPZ Datasheet - Page 8

• Manufacturer Part Number: ADCMP567BCPZ
• Description: IC COMP DUAL ULTRA-FAST 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: with Latchr

Specifications of ADCMP567BCPZ

• Number Of Elements: 2
• Output Type: Complementary, Differential, Open-Emitter, PECL
• Voltage - Supply: ±4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Comparator Type: High Speed
• No. Of Comparators: 2
• Response Time: 250ps
• Ic Output Type: Differential PECL, Open Emitter
• Supply Current: 13mA
• Rohs Compliant: Yes
• For Use With: EVAL-ADCMP567BCPZ - BOARD EVALUATION ADCMP567BCP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADCMP567
TIMING INFORMATION
The timing diagram in Figure 3 shows the ADCMP567 compare
and latch features. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol
t
t
t
t
PDH
PDL
PLOH
PLOL
Timing
Input to output
high delay
Input to output
low delay
Latch enable
to output high
delay
Latch enable
to output low
delay
INPUT VOLTAGE
LATCH ENABLE
LATCH ENABLE
DIFFERENTIAL
Q OUTPUT
Q OUTPUT
Description
Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output low-to-high transition
Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output high-to-low transition
Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output low-
to-high transition
Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output high-
to-low transition
V
IN
Figure 3. System Timing Diagram
V
t
S
OD
t
t
PDL
PDH
Rev. 0 | Page 8 of 16
t
H
t
R
Symbol
t
t
t
t
t
V
H
PL
S
R
F
OD
t
F
t
Timing
Minimum
hold time
Minimum
latch enable
pulsewidth
Minimum
setup time
Output rise
time
Output fall
time
Voltage
overdrive
PL
t
t
PLOH
PLOL
Description
Minimum time after the negative
transition of the Latch Enable
signal that the input signal must
remain unchanged to be acquired
and held at the outputs
Minimum time that the Latch
Enable signal must be high to
acquire an input signal change
Minimum time before the
negative transition of the Latch
Enable signal that an input signal
change must be present to be
acquired and held at the outputs
Amount of time required to
transition from a low to a high
output as measured at the 20%
and 80% points
Amount of time required to
transition from a high to a low
output as measured at the 20%
and 80% points
Difference between the
differential input and reference
input voltages
50%
V
50%
50%
REF
03633-0-003
± V
OS