ADM1169 Analog Devices, ADM1169 Datasheet - Page 19

• Manufacturer Part Number: ADM1169
• Description: Super Sequencer and Monitor with Margining Control and Non-Volatile Fault Recording
• Manufacturer: Analog Devices

Specifications of ADM1169

• # Supplies Monitored: 8
• Volt Monitoring Accuracy: 1%
• # Output Drivers: 8
• Fet Drive/enable Output: Both
• Voltage Readback: 12-bit ADC
• Supply Adj/margining: 12-bit ADC+4 DACs
• Package: 32 ld LQFP,40 ld LFCSP

SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 28 shows how the simple building block of a
single SE state can be used to build a power-up sequence for
a three-supply system. Table 8 lists the PDO outputs for each
state in the same SE implementation. In this system, a good 5 V
supply on the VP1 pin and the VX1 pin held low are the triggers
required to start a power-up sequence. The sequence next turns
on the 3.3 V supply, then the 2.5 V supply (assuming successful
turn-on of the 3.3 V supply). When all three supplies have turned
on correctly, the PWRGD state is entered, where the SE remains
until a fault occurs on one of the three supplies, or until it is
instructed to go through a power-down sequence by VX1
going high.
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following three sections (the Sequence
Detector section, the Monitoring Fault Detector section, and
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 28 to demonstrate
the actions of the state machine.
Sequence Detector
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the SE inputs
to change state, and it is most often used as the gate for successful
progress through a power-up or power-down sequence. A timer
block that is included in this detector can insert delays into a
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 27 is a block diagram of
the sequence detector.
Table 8. PDO Outputs for Each State
PDO Outputs
PDO1 = 3V3ON
PDO2 = 2V5ON
PDO3 = FAULT
VP1
VX4
(UNCONDITIONAL JUMP)
LOGIC INPUT CHANGE
OR FAULT DETECTION
SUPPLY FAULT
FORCE FLOW
DETECTION
WARNINGS
Figure 27. Sequence Detector Block Diagram
IDLE1
0
0
0
SELECT
IDLE2
0
0
0
INVERT
SEQUENCE
DETECTOR
EN3V3
1
0
0
TIMER
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EN2V5
1
1
0
If a timer delay is specified, the input to the sequence detector
must remain in the defined state for the duration of the timer
delay. If the input changes state during the delay, the timer is reset.
The sequence detector can also help to identify monitoring faults.
In the sample application shown in Figure 28, the FSEL1 and
FSEL2 states first identify which of the VP1, VP2, or VP3 pins
has faulted, and then they take appropriate action.
DIS3V3
0
1
1
VP1 = 0
MONITOR FAULT
FSEL2
VP2) = 0
STATES
(VP1 + VP2 + VP3) = 0
Figure 28. Sample Application Flow Diagram
VP2 = 0
(VP1 +
DIS2V5
1
0
1
(VP1 + VP2) = 0
FSEL1
VP3 = 0
VP1 = 0
SEQUENCE
PWRGD
1
1
0
PWRGD
STATES
EN3V3
EN2V5
IDLE1
IDLE2
VX1 = 0
VP1 = 1
VX1 = 1
VP3 = 1
VP2 = 1
10ms
20ms
VP2 = 0
DIS3V3
DIS2V5
FSEL1
1
1
1
TIMEOUT
STATES
VX1 = 1
VX1 = 1
ADM1169
FSEL2
1
1
1