ADM1073 Analog Devices, ADM1073 Datasheet - Page 7

• Manufacturer Part Number: ADM1073
• Description: -48 V Full Feature Hot Swap Controller
• Manufacturer: Analog Devices

Specifications of ADM1073

• I Control Accuracy %: 3%
• Other Inputs: RESTARTb,SHDNb
• Other Outputs: LATCHEDb,PWRGDb,SPLYGDb
• Package: 14-ld TSSOP
• Vin Min (v): -18V
• Vin Max (v): -80V
• Uv & Ov Detection: UV pin, OV pin

Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
RESTART
V
PWRGD
SS
SENSE
V
LATCHED
SPLYGD
GATE
DRAIN
OV
UV
TIMER
SHDN
IN
EE
profile. This pin can be overdriven to alter the current limit control loop threshold.
window.
Function
Input Pin. Edge-triggered 5-second shutdown and automatic restart.
Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via shunt resistor. A 1 µF
capacitor to V
Open Drain Output. Signals that the hot swap is complete.
Analog Pin for Soft Start. An external capacitor on this pin sets the ramp rate of the inrush current
Voltage Input from External Sense Resistor.
Ground Supply to Chip (usually a −48 V system supply). Also low-side sense resistor connection.
Open Drain Output. Signals the end of the PWM retry period after a current fault.
Open Drain Output. Signals that the device is not in reset and that the supply is in operating voltage
Output to External FET Gate Drive.
Analog Input for Monitoring of FET Drain Voltage.
Input Pin for Overvoltage Detection Circuitry.
Input Pin for Undervoltage Detection Circuitry.
Analog Pin. An external capacitor on this pin sets the maximum allowable time in current limit, the
PWM on-time, and the PWM duty cycle.
Input Pin. Level-triggered device shutdown and reset.
LATCHED
RESTART
PWRGD
EE
SENSE
is recommended on the V
V
V
SS
EE
IN
Figure 2. Pin Configuration
1
2
3
4
5
6
7
(Not to Scale)
ADM1073
Rev. A | Page 7 of 24
TOP VIEW
14
13
12
11
10
9
8
SHDN
TIMER
UV
OV
DRAIN
GATE
SPLYGD
IN
pin.
ADM1073