ADM1073 Analog Devices, ADM1073 Datasheet - Page 18

• Manufacturer Part Number: ADM1073
• Description: -48 V Full Feature Hot Swap Controller
• Manufacturer: Analog Devices

Specifications of ADM1073

• I Control Accuracy %: 3%
• Other Inputs: RESTARTb,SHDNb
• Other Outputs: LATCHEDb,PWRGDb,SPLYGDb
• Package: 14-ld TSSOP
• Vin Min (v): -18V
• Vin Max (v): -80V
• Uv & Ov Detection: UV pin, OV pin

ADM1073
FUNCTIONALITY AND TIMING
LIVE INSERTION
The timing waveforms associated with the live insertion of a
plug-in board using the ADM1073 are shown in Figure 36. The
long connector pins are the first to make connection, and the
GND − V
the voltage at the V
at this level with the shunt resistor and external resistor
combination at the V
staggered so that the R1/R2 and R3/R4 resistor dividers are the
last to connect to the backplane. This means that V
begin to ramp after the other pins connect. Note that staggered
connector pins are optional, because an internal time filter is
included on the UV pin.
When V
inside the operating voltage window and the −48 V supply must
be applied to the load. The SPLYGD output is asserted and after
a time delay, t
drive. When the voltage on the SENSE pin reaches 100 mV (the
analog current limit level), the gate drive is held constant. When
the board capacitance is fully charged, the sense voltage begins
to drop below the analog current limit voltage and the gate
voltage is free to ramp up further. The gate voltage eventually
climbs to its maximum value of 12.3 V and the PWRGD output
is asserted. Figure 37 shows some typical startup waveforms.
–48V RTN – VEE
Figure 36. Timing Waveforms Associated with a Live Insertion Event
SPLYGD
PWRGD
SENSE
GATE
V
UV
V
OUT
EE
V
UV
IN
crosses the undervoltage rising threshold, it is now
potential climbs to 48 V. As this voltage is applied,
POR
, the ADM1073 begins to ramp up the gate
V
IN
LKO
IN
pin ramps to a constant 12.3 V and is held
pin. In this case, the connection pins are
t
V
POR
UVR
UV
and V
OV
Rev. A | Page 18 of 24
OVERVOLTAGE AND UNDERVOLTAGE FAULTS
The waveforms for an overvoltage glitch are shown in Figure 38.
When V
overvoltage condition is detected and the GATE voltage is
pulled low. V
voltage window, and the GATE drive is restored when the
overvoltage falling threshold (1.93 V minus preset OV
hysteresis level) is reached. Figure 38 illustrates the ADM1073’s
reactions to an overvoltage condition.
Figure 38. Timing Waveforms Associated with an Overvoltage Fault
(Ch1 = GATE; Ch2 = SENSE; Ch3 = PWRGD ; Ch4 = SPLYGD )
OV
(Ch1 = GATE; Ch2 = OV; Ch3 = PWRGD ; Ch 4 = SPLYGD )
glitches above the overvoltage threshold of 1.93 V, an
OV
begins to drop back toward the operating
Figure 37. Typical Startup Sequence
Data Sheet