AD7951 Analog Devices, AD7951 Datasheet - Page 8

• Manufacturer Part Number: AD7951
• Manufacturer: Analog Devices

Specifications of AD7951

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Byte,Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7951
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1, 3, 42
2, 44
4
5
6
7
8
9, 10
11, 12
Mnemonic
AGND
AVDD
BYTESWAP
OB/2C
WARP
IMPULSE
SER/PAR
NC
D[0:1] or
DIVSCLK[0:1]
Type
P
P
DI
DI
DI
DI
DI
DO
DI/O
2
2
2
1
D0/DIVSCLK[0]
D1/DIVSCLK[1]
Description
Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be
referenced to AGND and should be connected to the analog ground plane of the system. In addition,
the AGND, DGND, and OGND voltages should be at the same potential.
Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
Parallel Mode Selection (8-Bit/14-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary.
When low, the MSB is inverted resulting in a twos complement output from its internal shift register.
Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following:
See the Modes of Operation section for a more detailed description.
Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the
Modes of Operation section for a more detailed description.
Serial/Parallel Selection Input.
When SER/PAR = low, the parallel mode is selected.
When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port
and the remaining data bits are high impedance outputs.
No Connect. Do not connect.
In parallel mode, these outputs are used as Bit 0 and Bit 1 of the parallel port data output bus.
Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial
data clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
NC = NO CONNECT
Conversion Mode
Normal
Impulse
Warp
Normal
BYTESWAP
IMPULSE
SER/PAR
AGND
OB/2C
WARP
AGND
AVDD
NC
NC
10
11
12
1
3
9
2
4
5
6
7
8
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
Figure 4. Pin Configuration
WARP
Low
Low
High
High
Rev. 0 | Page 8 of 32
(Not to Scale)
TOP VIEW
AD7951
IMPULSE
Low
High
Low
High
36
35
34
33
32
31
30
29
28
27
26
25
BIPOLAR
CNVST
PD
RESET
CS
RD
TEN
BUSY
D13/SCCS
D12/SCCLK
D11/SCIN
D10/HW/SW