SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 221
SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 221 of 248
- Download datasheet (2Mb)
B.1.7
ARM DDI0198D
Memory Region Remap Register
31
Bit
[3]
[2]
[1]
[0]
The read/write Memory Region Remap Register overrides the setting specified in the
MMU page tables, and the default behavior if the MMU is disabled.
The Memory Region Register has four fields for remapping instruction-side memory
regions and four fields for remapping data-side memory regions.
You can access the Memory Region Remap Register with the instructions in
Table B-11.
Figure B-9 shows the bit fields of the Memory Region Remap Register.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Name
DIUTM
DDUTM
DIUTL
DDUTL
Table B-10 MMU Debug Control Register bit assignments (continued)
SBZ
Function
Disable instruction micro TLB match
Disable data micro TLB match
Disable instruction micro TLB load
Disable data micro TLB load
Instruction
Table B-11 Memory Region Remap Register instructions
Figure B-9 Memory Region Remap Register format
16
15
IWB
14
13
IWT
12 11
Operation
Read Memory Region Remap Register
Write Memory Region Remap Register
INCNB
INCB
10
Description
0 = Enable I-micro TLB load
1 = Disable I-micro TLB load
0 = Enable D-micro TLB match
1 = Disable D-micro TLB match
0 = Enable D-micro TLB load
1 = Disable D-micro TLB load
0 = Enable I-micro TLB load
1 = Disable I-micro TLB load
CP15 Test and Debug Registers
9
8 7
DWB
DNCNB
6
DNCB
DWT
5
4 3
2
1
B-15
0
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