ATtiny861 Automotive Atmel Corporation, ATtiny861 Automotive Datasheet - Page 133
ATtiny861 Automotive
Manufacturer Part Number
ATtiny861 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY261_AUTOMOTIVE.pdf
(11 pages)
3.ATTINY261_AUTOMOTIVE.pdf
(16 pages)
4.ATTINY261_AUTOMOTIVE.pdf
(226 pages)
Specifications of ATtiny861 Automotive
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY261_AUTOMOTIVE PDF datasheet #2
- ATTINY261_AUTOMOTIVE PDF datasheet #3
- ATTINY261_AUTOMOTIVE PDF datasheet #4
- Current page: 133 of 226
- Download datasheet (5Mb)
7753F–AVR–01/11
Figure 17-4. Two-wire Mode Operation, Simplified Diagram
Figure 17-4
It is only the physical layer that is shown since the system operation is highly dependent of the
communication scheme used. The main differences between the Master and Slave operation at
this level, is the serial clock generation which is always done by the Master, and only the Slave
uses the clock control unit. Clock generation must be implemented in software, but the shift
operation is done automatically by both devices. Note that only clocking on negative edge for
shifting data is of practical use in this mode. The slave can insert wait states at start or end of
transfer by forcing the SCL clock low. This means that the Master must always check if the SCL
line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that the
transfer is completed. The clock is generated by the master by toggling the USCK pin via the
PORT Register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
Figure 17-5. Two-wire Mode, Typical Timing Diagram
SDA
SCL
SLAVE
MASTER
shows two USI units operating in Two-wire mode, one as Master and one as Slave.
Bit7
Bit7
S
A B
Bit6
Bit6
Bit5
Bit5
C
ADDRESS
1 - 7
Bit4
Bit4
Bit3
Bit3
R/W
8
Bit2
Bit2
ATtiny261/ATtiny461/ATtiny861
D
Bit1
Bit1
ACK
9
Bit0
Bit0
E
DATA
1 - 8
Two-wire Clock
Control Unit
ACK
9
PORTxn
DATA
1 - 8
HOLD
SCL
SDA
SCL
SDA
SCL
ACK
9
VCC
F
P
133
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