ATmega8535 Atmel Corporation, ATmega8535 Datasheet - Page 126

• Manufacturer Part Number: ATmega8535
• Manufacturer: Atmel Corporation

Specifications of ATmega8535

• Flash (kbytes): 8 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Timer/Counter Timing
Diagrams
126
ATmega8535(L)
between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
The “N” variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
At the very start of period 2 in Figure 59 OCn has a transition from high to low even
though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
•
•
The following figures show the Timer/Counter in Synchronous mode, and the Timer
Clock (clk
should be replaced by the Timer/Counter Oscillator clock. The figures include informa-
tion on when interrupt flags are set. Figure 60 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value
in all modes other than phase correct PWM mode.
Figure 60. Timer/Counter Timing Diagram, no Prescaling
Figure 61 shows the same timing data, but with the prescaler enabled.
TCNTn
(clk
TOVn
clk
clk
I/O
OCR2 changes its value from MAX, like in Figure 59. When the OCR2 value is MAX
the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the
result of an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCR2, and for that
reason misses the Compare Match and hence the OCn change that would have
happened on the way up.
I/O
Tn
/1)
T2
) is therefore shown as a clock enable signal. In Asynchronous mode, clk
MAX - 1
f
OCnPCPWM
MAX
=
----------------- -
N 510
f
clk_I/O
⋅
BOTTOM
2502K–AVR–10/06
BOTTOM + 1
I/O