AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 42

no-image

AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A3128-ALUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
135
Part Number:
AT32UC3A3128-ALUT
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT32UC3A3128-CTUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT32UC3A3128-CTUT
Manufacturer:
Atmel
Quantity:
1 801
Part Number:
AT32UC3A3128-CTUT
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT32UC3A3128-CTUT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT32UC3A3128-U
Manufacturer:
ATMEL
Quantity:
11
5.2.3
5.2.4
42
AVR32
Page Table Organization
TLB organization
The MMU leaves the page table organization up to the OS software. Since the page table han-
dling and TLB handling is done in software, the OS is free to implement different page table
organizations. It is recommended, however, that the page table entries (PTEs) are of the format
shown in Figure 5-4. This allows the loaded PTE to be written directly into TLBELO, without the
need for reformatting. How the PTEs are indexed and organized in memory is left to the OS.
Figure 5-4.
The TLB is used as a cache for the page table, in order to speed up the virtual memory transla-
tion process. Up to two TLBs can be implemented, each with up to 64 entries. Each TLB is
configured as shown in
Figure 5-5.
The D, W and AP[1] bits are not implemented in ITLBs, since they have no meaning there.
The AP[0] bits are not implemented in DTLBs, since they have no meaning there.
The A bit is the Accessed bit. This bit is set when the TLB entry is loaded with a new value using
the tlbw instruction. It is cleared whenever the TLB matching process finds a match in the spe-
cific TLB entry. The A bit is used to implement pseudo-LRU replacement algorithms.
When an address look-up is performed by the TLB, the address section is searched for an entry
matching the virtual address to be accessed. The matching process is described in chapter
5.2.5.
Entry 63
Entry 0
Entry 1
Entry 2
Entry 3
31
Recommended Page Table Entry format
TLB organization
VPN[21:0]
VPN[21:0]
VPN[21:0]
VPN[21:0]
VPN[21:0]
Address section
Figure 5-5 on page
ASID[7:0]
ASID[7:0]
ASID[7:0]
ASID[7:0]
ASID[7:0]
PFN
42.
V
V
V
V
V
PFN[21:0]
PFN[21:0]
PFN[21:0]
PFN[21:0]
PFN[21:0]
Data section
C
C
C
C
C
10
G
G
G
G
G
C
9
B
B
B
B
B
8 7 6
G
AP[2:0]
AP[2:0]
AP[2:0]
AP[2:0]
AP[2:0]
B
AP
SZ[1:0]
SZ[1:0]
SZ[1:0]
SZ[1:0]
SZ[1:0]
4 3 2 1
32000D–04/2011
SZ
D
D
D
D
D
D
W
W
W
W
W
W
0
A
A
A
A
A

Related parts for AT32UC3A3128