AT32UC3A0256AU Atmel Corporation, AT32UC3A0256AU Datasheet - Page 23
AT32UC3A0256AU
Manufacturer Part Number
AT32UC3A0256AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0256AU
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
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Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- AT32UC3A0128AU PDF datasheet #6
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- Download datasheet (5Mb)
32000D–04/2011
Table 2-8.
Table 2-9 on page 23
Table 2-9.
Name
S
D
R
Name
IMMU SZ
DMMU SZ
CONFIG0 Fields (Continued)
CONFIG1 Fields
Bit
2
1
0
Bit
31:26
25:20
shows the CONFIG1 fields.
Description
SIMD instructions implemented
Value
0
1
DSP instructions implemented
Value
0
1
Memory Read-Modify-Write instructions implemented
Value
0
1
Description
The number of entries in the IMMU equals (IMMU SZ) + 1. Not used
in single-MMU or MPU systems.
Specifies the number of entries in the DMMU or in the shared MMU in
single-MMU systems. The number of entries in the DMMU or shared
MMU equals (DMMU SZ + 1). In systems with MPU, DMMU SZ
equals the number of MPUAR entries.
Semantic
No SIMD instructions
SIMD instructions implemented
Semantic
No DSP instructions
DSP instructions implemented
Semantic
No RMW instructions
RMW instructions implemented
AVR32
23
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