RTL8139C RETEK, RTL8139C Datasheet

no-image

RTL8139C

Manufacturer Part Number
RTL8139C
Description
25 MHz, 3.3 V single chip fast ethernet controller with power management
Manufacturer
RETEK
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
RTL8139C
Quantity:
198
Part Number:
RTL8139C
Manufacturer:
RMC
Quantity:
1 000
Part Number:
RTL8139C
Manufacturer:
RMC
Quantity:
20 000
Part Number:
RTL8139C+
Manufacturer:
EPSON
Quantity:
1 831
Part Number:
RTL8139C+
Manufacturer:
REALTEK
Quantity:
200
Part Number:
RTL8139C-LF
Manufacturer:
REALTEK10
Quantity:
436
Part Number:
RTL8139C-LF
Manufacturer:
REALTEK11
Quantity:
13 539
Part Number:
RTL8139CL
Manufacturer:
RMC
Quantity:
13
Part Number:
RTL8139CL
Manufacturer:
RTL
Quantity:
1 000
Part Number:
RTL8139CL
Manufacturer:
RMC
Quantity:
1 000
Part Number:
RTL8139CL
Manufacturer:
REALTEK
Quantity:
1 000
Part Number:
RTL8139CL
Manufacturer:
RTL
Quantity:
1 000
Part Number:
RTL8139CL
Manufacturer:
RMC
Quantity:
20 000
Part Number:
RTL8139CL+
Manufacturer:
REALTEK/瑞昱
Quantity:
20 000
2002/01/10
1. Features: .................................................................. 2
2. General Description................................................ 3
3. Block Diagram ........................................................ 4
4. Pin Assignments...................................................... 5
5. Pin Descriptions ...................................................... 6
6. Register Descriptions............................................ 10
7. EEPROM Contents .............................................. 33
FAST ETHERNET CONTROLLER
5.1 Power Management/Isolation Interface .............. 6
5.2 PCI Interface....................................................... 6
5.3 FLASH/EEPROM Interface ............................... 8
5.4 Power Pins .......................................................... 9
5.5 LED Interface ..................................................... 9
5.6 Attachment Unit Interface .................................. 9
5.7 Test and Other Pins............................................. 9
6.1 Receive Status Register in Rx packet header.... 12
6.2 Transmit Status Register................................... 13
6.3 ERSR: Early Rx Status Register....................... 14
6.4 Command Register ........................................... 14
6.5 Interrupt Mask Register .................................... 15
6.6 Interrupt Status Register ................................... 15
6.7 Transmit Configuration Register ...................... 16
6.8 Receive Configuration Register........................ 17
6.9 9346CR: 93C46 (93C56) Command Register ......... 19
6.10 CONFIG 0: Configuration Register 0............. 20
6.11 CONFIG 1: Configuration Register 1............. 21
6.12 Media Status Register ..................................... 22
6.13 CONFIG 3: Configuration Register3.............. 22
5.14 CONFIG 4: Configuration Register4.............. 24
6.15 Multiple Interrupt Select Register..................... 25
6.16 PCI Revision ID.............................................. 25
6.17 Transmit Status of All Descriptors (TSAD) Register......... 25
6.18 Basic Mode Control Register.......................... 26
6.19 Basic Mode Status Register ............................ 26
6.20 Auto-negotiation Advertisement Register.............. 27
6.21 Auto-Negotiation Link Partner Ability Register............... 27
6.22 Auto-negotiation Expansion Register .............. 28
6.23 Disconnect Counter ........................................ 28
6.24 False Carrier Sense Counter ........................... 28
6.25 NWay Test Register........................................ 28
6.26 RX_ER Counter.............................................. 29
6.27 CS Configuration Register.............................. 29
6.28 Flash Memory Read/Write Register ........................ 29
6.29 Config5: Configuration Register 5 ................. 30
6.30 Function Event Register ................................. 31
6.31 Function Event Mask Register........................ 31
6.32 Function Present State Register ...................... 32
6.33 Function Force Event Register ....................... 32
WITH POWER MANAGEMENT
REALTEK 3.3V SINGLE CHIP
RTL8139C(L)
1
8. PCI Configuration Space Registers..................... 36
9. Functional Description ......................................... 46
10. Application Diagram .......................................... 50
11. Electrical Characteristics ................................... 51
12. Mechanical Dimensions ...................................... 60
7.1 Summary of EEPROM Registers ............................. 35
7.2 Summary of EEPROM Power Management Registers....... 35
8.1 PCI Configuration Space Table ........................ 36
8.2 PCI Configuration Space Functions.................. 37
8.3 Default Values After Power-on (RSTB asserted)...... 42
8.4 PCI Power Management Functions .................. 43
8.5 Vital Product Data (VPD)................................. 45
9.1 Transmit Operation ........................................... 46
9.2 Receive Operation............................................. 46
9.3 Line Quality Monitor ........................................ 46
9.4 Clock Recovery Module ................................... 46
9.5 Loopback Operation ......................................... 46
9.6 Tx Encapsulation .............................................. 46
9.7 Collision............................................................ 46
9.8 Rx Decapsulation.............................................. 47
9.9 Flow Control..................................................... 47
9.10 LED Functions................................................ 47
11.1 Temperature Limit Ratings ............................. 51
11.2 DC Characteristics .......................................... 51
11.3 AC Characteristics .......................................... 52
9.9.1. Control Frame Transmission..................... 47
9.9.2. Control Frame Reception .......................... 47
9.10.1 10/100 Mbps Link Monitor...................... 47
9.10.2 LED_RX .................................................. 48
9.10.3 LED_TX .................................................. 48
9.10.4 LED_TX+LED_RX................................. 49
11.2.1 Supply Voltage ........................................ 51
11.3.1 FLASH/BOOT ROM Timing .................. 52
11.3.2 PCI Bus Operation Timing: ..................... 54
RTL8139C(L)
Rev.1.4

Related parts for RTL8139C

RTL8139C Summary of contents

Page 1

... Control Frame Transmission..................... 47 9.9.2. Control Frame Reception .......................... 47 9.10 LED Functions................................................ 47 9.10.1 10/100 Mbps Link Monitor...................... 47 9.10.2 LED_RX .................................................. 48 9.10.3 LED_TX .................................................. 48 9.10.4 LED_TX+LED_RX................................. 49 10. Application Diagram .......................................... 50 11. Electrical Characteristics ................................... 51 11.1 Temperature Limit Ratings ............................. 51 11.2 DC Characteristics .......................................... 51 11.2.1 Supply Voltage ........................................ 51 11.3 AC Characteristics .......................................... 52 11.3.1 FLASH/BOOT ROM Timing .................. 52 11.3.2 PCI Bus Operation Timing: ..................... 54 12. Mechanical Dimensions ...................................... 60 1 RTL8139C(L) Rev.1.4 ...

Page 2

... Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse) Note: The model number of the QFP package is RTL8139C. The LQFP package model number is RTL8139CL. 2002/01/10 Supports auxiliary power-on internal reset ready for remote wake-up when main power still remains off ...

Page 3

... RTL8139C(L) can be shut down temporarily according to user requirements or when the RTL8139C( power down state with the wakeup function disabled. In addition, when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning and power consumption of the RTL8139C(L) will be negligible ...

Page 4

... Transmit/ FIFO Receive Logic Logic Interface Descrambler Scrambler Link pulse 10M Output waveform shaping Receive low pass filter 3 Level Driver Peak Detect Adaptive Equalizer Master PPL 25M RTL8139C(L) MII Interface RXD RXC 25M TXD TXC 25M TXO+ TXO - RXIN+ RXIN- Rev.1.4 ...

Page 5

... CBE3B 3 IDSEL 4 AD23 5 AD22 6 AD21 7 GND 8 AD20 9 AD19 10 AD18 11 AD17 12 VDD 13 AD16 14 CBE2B 15 FRAMEB 16 IRDYB 17 TRDYB 18 GND 19 DEVSELB 2002/01/10 RTL8139C(L) 5 RTL8139C(L) 83 LWAKE/CSTSCHG 82 RTT2 81 RTT3 80 GND VDD 76 PMEB 75 CLKRUNB 74 GND MA16 69 MA15 68 MA14 67 MA13 66 MA12 65 MA11 64 MA10 ...

Page 6

... Isolate Pin: Active low. Used to isolate the RTL8139C(L) from the PCI bus. The RTL8139C(L) does not drive its PCI outputs (excluding PME#) and does not sample its PCI input (including RST# and PCICLK) as long as the Isolate pin is asserted ...

Page 7

... As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it. 117 Grant: This signal is asserted low to indicate to the RTL8139C(L) that the central arbiter has granted ownership of the bus to the RTL8139C(L). This input is used when the RTL8139C(L) is acting as a bus master ...

Page 8

... After the host clears the system error, the RTL8139C(L) continues its operation. When the RTL8139C(L) is the bus target and a parity error is detected, the RTL8139C(L) asserts this PERRB pin low. 22 ...

Page 9

... Crystal Feedback Output: This output is used in crystal connection only. It must be left open when X1 is driven with an external 25 MHz oscillator. Pin No 81, 82 Chip test pins. 84 This pin must be pulled low by a 1.7KΩ resistor. Reserved 9 RTL8139C(L) Description Description Tx/Rx Tx/Rx Tx LINK100 LINK10/100 LINK10/100 ...

Page 10

... Register Descriptions The RTL8139C(L) provides the following set of operational registers mapped into PCI memory space or I/O space. Offset R/W 0000h R/W 0001h R/W 0002h R/W 0003h R/W 0004h R/W 0005h R/W 0006h-0007h - 0008h R/W 0009h R/W 000Ah R/W 000Bh R/W 000Ch R/W 000Dh R/W 000Eh R/W 000Fh R/W 0010h-0013h R/W 0014h-0017h R/W 0018h-001Bh R/W 001Ch-001Fh R/W 0020h-0023h R/W 0024h-0027h R/W 0028h-002Bh R/W 002Ch-002Fh R/W 0030h-0033h ...

Page 11

... LSB of the Mask byte of Wakeup Frame4 Within Offset LSBCRC5 LSB of the Mask byte of Wakeup Frame5 Within Offset LSBCRC6 LSB of the Mask byte of Wakeup Frame6 Within Offset LSBCRC7 LSB of the Mask byte of Wakeup Frame7 Within Offset FLASH Flash Memory Read/Write Register 11 RTL8139C(L) Rev.1.4 ...

Page 12

... CRC CRC Error: When set, indicates that a CRC error occurred on the received packet. FAE Frame Alignment Error: When set, indicates that a frame alignment error occurred on this received packet. ROK Receive OK: When set, indicates that a good packet is received. 12 RTL8139C(L) Description Rev.1.4 ...

Page 13

... Transmit Status Register (TSD0-3)(Offset 0010h-001Fh, R/W) The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8139C(L) when the Transmit Byte Count (bit12-0) in the corresponding Tx descriptor is written not affected when software writes to these bits. These registers are only permitted to write by double-word access. After a software reset, all bits except the OWN bit are reset to “0”. ...

Page 14

... R 6.4 Command Register (Offset 0037h, R/W) This register is used for issuing commands to the RTL8139C(L). These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here. Bit R/W ...

Page 15

... Receive Error Interrupt: 1 => Enable, 0 => Disable. ROK Receive OK Interrupt: 1 => Enable, 0 => Disable. Symbol SERR System Error: Set to 1 when the RTL8139C(L) signals a system error on the PCI bus. TimeOut Time Out: Set to 1 when the TCTR register reaches to the value of the TimerInt register. ...

Page 16

... Transmit Configuration Register (Offset 0040h-0043h, R/W) This register defines the Transmit Configuration for the RTL8139C(L). It controls such functions as Loopback, Heartbeat, Auto Transmit Padding, programmable Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size. Bit R 30-26 R 25-24 R 22-19 - 18, 17 R/W 16 R/W 15-11 - 10-8 R/W 2002/01/10 Symbol - Reserved ...

Page 17

... R/W 3 6.8 Receive Configuration Register (Offset 0044h-0047h, R/W) This register is used to set the receive configuration for the RTL8139C(L). Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Bit R/W 31-28 - 27-24 R/W 23- R/W 16 R/W 15-13 R/W 2002/01/10 TXRR Tx Retry Count: These are used to specify additional transmission retries in multiples of 16 (IEEE 802 ...

Page 18

... Rx buffer and the transfer has arrived at the end of the Rx buffer. 1: The RTL8139C(L) will keep moving the rest of the packet data into the memory immediately after the end of the Rx buffer, if this packet has not been completely moved into the Rx buffer and the transfer has arrived at the end of the Rx buffer ...

Page 19

... Accept Physical Address Packets: This bit allows the receiver to accept or reject packets with a physical destination address. 0: Reject packets with a physical destination address 1: Accept packets with a physical destination address Symbol EEM1-0 Operating Mode: These 2 bits select the RTL8139C(L) operating mode. EEM1 EEM0 ...

Page 20

... T10 10 Mbps Mode: Always 0. PL1, PL0 Select 10 Mbps medium type: Always (PL1, PL0) = (1, 0) BS2, BS1, BS0 Select Boot ROM size BS2 RTL8139C(L) Description BS1 BS0 Description Boot ROM Boot ROM 1 0 16K Boot ROM 1 1 ...

Page 21

... Writing Writing When the command register bits IOEN, MEMEN, and BMEN of the PCI configuration space are written, the RTL8139C(L) will clear this bit automatically. LWAKE active mode: The LWACT bit and LWPTN bit in the CONFIG4 register are used to program the LWAKE pin’s output signal. According to the combination of these two bits, there may be 4 choices of LWAKE signal, i ...

Page 22

... TXPF Transmit Pause Flag: Set when the RTL8139C(L) sends pause packet. Reset when the RTL8139C(L) sends timer done packet. RXPF Receive Pause Flag: Set when the RTL8139C( backoff state because a pause packet received. Reset when pause state is clear. Symbol GNTSel Gnt Select: Select the Frame’ ...

Page 23

... Magic Magic Packet: This bit is valid when the PWEn bit of CONFIG1 register is set. The RTL8139C(L) will assert the PMEB signal to wakeup the operating system when the Magic Packet is received. Once the RTL8139C(L) has been enabled for Magic Packet wakeup and has been put into adequate state, it scans all incoming packets addressed to the node for a specific data sequence, which indicates to the controller that this is a Magic Packet frame ...

Page 24

... The wake-up frame 4 and 5, 6 and 7 are merged respectively into another 2 long wake-up frames. Please refer to 7.4 PCI Power Management functions for a detailed description. Set to 0: The RTL8139C(L) supports wake-up frames, each with masked bytes selected from offset 12 to 75. LWPME LANWAKE vs. PMEB: Set to 1: The LWAKE can only be asserted when the PMEB is asserted and the ISOLATEB is low ...

Page 25

... Multiple Interrupt Select Register (Offset 005Ch-005Dh, R/W) If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to RTL8139C(L), RCR<ERTH[3:0]> will not be used to transfer data in early mode. This register will be written to the received data length in order to make an early Rx interrupt for the unfamiliar protocol. ...

Page 26

... Link had been experienced fail state 1 = valid link established valid link established jabber condition detected jabber condition detected extended register capability basic register capability only. 26 RTL8139C(L) Default/ Attribute ...

Page 27

... Link Partner's binary encoded node selector. Currently only CSMA/ CD <00001> is specified. 27 RTL8139C(L) Default/ Attribute The default value ...

Page 28

... Description/Usage Reserved 1 = set NWay to loopback mode. Reserved 1 = LED0 Pin indicates linkpulse 1 = Auto-neg experienced ability detect state 1 = Auto-neg experienced parallel detection fault state 1 = Auto-neg experienced link status check state 28 RTL8139C(L) Default/ Attribute - Default/ Attribute h'[0000], ...

Page 29

... Disable read/write access to flash memory via software. 1: Enable read/write access to flash memory via software and disable the EEPROM access during flash memory access via software. Flash Memory Address Bus: These bits set the state of the MA16-0 pins. 29 RTL8139C(L) Default/ Attribute h'[0000], R Default/ Attribute 0,WO ...

Page 30

... R/W 1 R/W 0 R/W Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer supported by RTL8139C.) The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8139C Config5 register. 2002/01/10 Symbol - Reserved BWF Broadcast Wakeup Frame: 0: Default value. Disable Broadcast Wakeup Frame with mask bytes of only DID field = ...

Page 31

... Function Event Register will not cause the CSTSCHG pin to be asserted. Setting this bit to 1, enables the GWAKE field in the Function Event Register to assert CSTSCHG pin if bit14 of this register is also set. This bit is not affected by RST#. - Reserved 31 RTL8139C(L) Description Description Rev.1.4 ...

Page 32

... General Wakeup: Setting this bit to 1, sets the GWAKE bit in the Function Event Register. However, the GWAKE bit in the Function Present State Register is not affected and continues to reflect the current state of the Wakeup request. Writing this bit has no effect. - Reserved 32 RTL8139C(L) Description Description Rev.1.4 ...

Page 33

... After the valid duration of the RSTB pin or auto-load command in 9346CR, the RTL8139C(L) performs a series of EEPROM read operations from the 93C46 (93C56) address 00H to 31H suggested to obtain Realtek approval before changing the default settings of the EEPROM. ...

Page 34

... Reserved. Do not change this field without Realtek approval. PHY Parameter 1-T for RTL8139C. Operational registers of the RTL8139C(L) are from 78h to 7Bh. Reserved. Do not change this field without Realtek approval. PHY Parameter 2-T for RTL8139C. Operational register of the RTL8139C(L) is 80h. Reserved. Reserved. Do not change this field without Realtek approval. CIS Pointer. ...

Page 35

... Spd_Set - - Spd_Set GNTDel PARM_EN Magic - PARM_EN Magic AnaOff LongWF AutoClr Bit7 Bit6 Bit5 Aux_I_b1 Aux_I_b0 DSI PME_D3 PME_D3 PME_D2 PME_D1 PME_D0 cold ho t PME_Status - - PME_Status - - 35 RTL8139C(L) Bit4 Bit3 Bit2 - - BS2 - - - - - - - - - - - ANE - - ANE - - LinkUp CardB_En CLKRU N_En LinkUp - - LWPME - LWPTN 32 bit Read Write ...

Page 36

... SVID4 SVID3 SVID2 SVID12 SVID11 SVID10 SMID4 SMID3 SMID2 SMID12 SMID11 SMID10 ILR4 ILR3 ILR2 RTL8139C(L) Bit1 Bit0 VID1 VID0 VID9 VID8 DID1 DID0 DID9 DID8 MEMEN IOEN MEMEN IOEN FBTBEN SERREN - SERREN 0 0 DST0 DPD - DPD ...

Page 37

... PCI Configuration Space Functions The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The functions of RTL8139C(L)'s configuration space are described below. VID: Vendor ID. This field will be set to a value corresponding to PCI Vendor ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI Vendor ID ...

Page 38

... Special Cycle Enable: Read as 0, write operation has no effect. The RTL8139C(L) ignores all special cycle operation. 2 BMEN Bus Master Enable: When set to 1, the RTL8139C(L) is capable of acting as a bus master. When set prohibited from acting as a PCI bus master. For the normal operation, this bit must be set by the system BIOS. 1 MEMEN Memory Space Access: When set to 1, the RTL8139C(L) responds to memory space accesses ...

Page 39

... Because the PCI version 2.1 specification does not define any specific value for network devices, PIFR = 00h. SCR: Sub-Class Register The Sub-class register is an 8-bit register that identifies the function of the RTL8139C(L). SCR = 00h indicates that the RTL8139C( Ethernet controller. ...

Page 40

... Reserved 0 IOIN IO Space Indicator: Read only. Set the RTL8139C(L) to indicate that it is capable of being mapped into IO space. MEMAR: This register specifies the base memory address for memory accesses to the RTL8139C(L) operational registers. This register must be initialized prior to accessing any of the RTL8139C(L)'s register with memory access. ...

Page 41

... SMID: Subsystem ID. This field will be set to a value corresponding to the PCI Subsystem ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 8129h. BMAR: This register specifies the base memory address for memory accesses to the RTL8139C(L) operational registers. This register must be initialized prior to accessing any of the RTL8139C(L)'s registers with memory access. ...

Page 42

... RTL8139C(L) uses INTA interrupt pin. Read only. IPR = 01H. MNGNT: Minimum Grant Timer: Read only Specifies how long a burst period the RTL8139C(L) needs at 33 MHz clock rate in units of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h. ...

Page 43

... The Rx state machine is stopped, and the RTL8139C(L) keeps monitoring the network for wakeup events such as Magic Packet, Wakeup Frame, and/or Link Change, in order to wake up the system. When in power down mode, the RTL8139C(L) will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx FIFO. ...

Page 44

... PMC 76 not recommended to set the D0_support_PME bit to “1”. A Link Wakeup occurs only when the following conditions are met: ♦ The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8139C( isolation state, or the PME# can be asserted in current power state. ♦ ...

Page 45

... VPD data register and the 93C46/93C56 has been completed or not. 1. Write VPD register: (write data to 93C46/93C56)Write the flag bit to a one at the same time the VPD address is written. When the flag bit is set to zero by the RTL8139C(L), the VPD data (all 4 bytes) has been transferred from the VPD data register to 93C46/93C56. 2. ...

Page 46

... The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the entire packet has been transferred to the Tx buffer, the RTL8139C(L) is instructed to move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a complete packet or is filled to the programmed threshold level, the RTL8139C(L) begins packet transmission ...

Page 47

... After detecting receive activity on the line, the RTL8139C(L) starts to process the preamble bytes based on the mode of operation. While operating in 100Base-TX mode, the RTL8139C(L) expects the frame to start with the symbol pair JK in the first bye of the 8-byte preamble. The RTL8139C(L) checks the CRC bytes and checks if the packet data ends with the TR symbol pair, if not, the RTL8139C(L) reports a CRC error RSR. The RTL8139C(L) reports a RSR< ...

Page 48

... In 10/100 Mbps mode, the LED function is like the RTL8129. 9.10.3 LED_TX 2002/01/10 Power On LED = Low No Receiving Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Power On LED = Low No Transmitting Packet Yes LED = High for (100 +- 10) ms LED = Low for ( RTL8139C(L) Rev.1.4 ...

Page 49

... LED_TX+LED_RX 2002/01/10 Power On LED = Low Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( RTL8139C(L) Rev.1.4 ...

Page 50

... Application Diagram RJ45 Magetics 2002/01/10 EEPROM LED CLK RTL8139C(L) Auxiliary Power PCI INTERFACE 50 RTL8139C(L) DATA BOOT ROM Address Rev.1.4 ...

Page 51

... I CC Average Operating Supply Current 2002/01/10 Minimum Maximum -55 +125 0 70 Conditions Minimum I OH= -8mA 0.9 * Vcc I OL= 8mA 0.5 * Vcc -0 -1.0 GND V OUT -10 GND I OUT= 0mA, 51 RTL8139C(L) Units °C °C Maximum Units Vcc V 0.1 * Vcc V Vcc+0.5 V 0.3 * Vcc V 1 150 mA Rev.1.4 ...

Page 52

... TOHZ Output Disable to Output in High Z TOH Output Hold from Address, ROMCSB, or OEB TWRBR Write Recovery time Before Read 2002/01/10 TRC TWRBR TOES TCE TOOLZ TCOLZ TACC Minimum 135 - - - RTL8139C(L) TOHZ TOH Typical Maximum Units - - - 200 - 200 - Rev.1 ...

Page 53

... Minimum 53 PROGRAM VERIFY VERIFICATION COMMAND tRC tAH tCH tWHGL tWP tOE tDS tDH tOOLZ DATAOUT =C0H tCOLZ tCE Typical Maximum 135 - RTL8139C(L) STANDBY/VCC POWER-DOWN tDF tOH VALID DATA IN Units - Rev.1.4 ...

Page 54

... PCI Bus Operation Timing: 2002/01/10 Target Read Target Write 54 RTL8139C(L) Rev.1.4 ...

Page 55

... Configuration Read Configuration Write 55 RTL8139C(L) Rev.1.4 ...

Page 56

... BUS Arbitration Memory Read 56 RTL8139C(L) Rev.1.4 ...

Page 57

... Memory Write Target Initiated Termination - Retry 57 RTL8139C(L) Rev.1.4 ...

Page 58

... Target Initiated Termination - Disconnect Target Initiated Termination - Abort 58 RTL8139C(L) Rev.1.4 ...

Page 59

... Master Initiated Termination - Abort Parity Operation - one example 59 RTL8139C(L) Rev.1.4 ...

Page 60

... Dimension b does not include dambar protrusion/intrusion 3.40 3. Controlling dimension: Millimeter 0.91 4. General appearance spec. should be based on final visual 0.25 2.85 3.10 inspection spec. 0.22 0.32 0.15 0.25 TITLE: 128 QFP (14x20 mm ) PACKAGE OUTLINE 0.5 0.75 APPROVE 0.88 1.08 1.60 1.85 CHECK - - 0.10 - REALTEK SEMI-CONDUCTOR CO., LTD 12° 60 RTL8139C(L) -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL: DOC. NO. 530-ASS-P004 VERSION PAGE DWG NO. Q128 - 1 DATE Nov. 4 1999 1 OF Rev.1.4 ...

Page 61

... Millimeter - - 1.70 3.General appearance spec. should be based on final visual - 0.25 1.40 1.50 0.29 0.22 - 0.20 TITLE: 128LD LQFP ( 14x20x1.4 mm*2 ) PACKAGE 14.25 20.25 0.50 BSC APPROVE 16.30 23.30 0.75 CHECK 0.60 1.00 REF 0° 3.5° 9° 61 -CU L/F, FOOTPRINT 2.0 mm LEADFRAME MATERIAL: DOC. NO. VERSION PAGE DWG NO. DATE REALTEK SEMICONDUCTOR CORP. RTL8139C(L) 530-ASS-P004 1 OF LQ128 - 1 Nov. 4.1999 Rev.1.4 ...

Page 62

... Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2002/01/10 62 RTL8139C(L) Rev.1.4 ...

Related keywords