HD6432127RFA Renesas Electronics Corporation., HD6432127RFA Datasheet

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HD6432127RFA

Manufacturer Part Number
HD6432127RFA
Description
Single-Chip Microcomputer
Manufacturer
Renesas Electronics Corporation.
Datasheet

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To all our customers
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003

Related parts for HD6432127RFA

HD6432127RFA Summary of contents

Page 1

To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...

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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...

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Hitachi 16-Bit Single-Chip Microcomputer H8S/2128 Series, H8S/2124 Series H8S/2128F-ZTAT™ ADE-602-114B Rev. 3.0 5/22/02 Hitachi, Ltd. Hardware Manual — Supplement — ...

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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...

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Announcement of Changes to Hardware Manual Contents This is to announce that, with the addition of H8S/2128S and H8S/2127S products, a Supplement has been prepared for the following sections of the Hitachi single-chip microcomputer H8S/2128 Series and H8S/2124 Series Hardware ...

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Section Bus Interface [Option] 16.1 Overview ............................................................................................................................ 16.1.1 Features ................................................................................................................. 16.1.2 Block Diagram ...................................................................................................... 16.1.3 Input/Output Pins .................................................................................................. 16.1.4 Register Configuration .......................................................................................... 16.2 Register Descriptions.......................................................................................................... 2 16.2 Bus Data Register (ICDR) .............................................................................. 16.2.2 Slave ...

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Electrical Characteristics [H8S/2128S Series] ................................................................... 95 22.3.1 Absolute Maximum Ratings.................................................................................. 95 22.3.2 DC Characteristics ................................................................................................ 96 22.3.3 AC Characteristics ................................................................................................ 107 22.3.4 A/D Conversion Characteristics............................................................................ 126 22.3.5 Usage Note ............................................................................................................ 128 22.4 Electrical Characteristics [H8S/2124 Series] ..................................................................... 130 22.4.1 ...

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Section two-channel I C bus interface is available as an option in the H8S/2128 Series. The I interface is not available for the H8S/2124 Series. Observe the following notes when using this option. 1. For mask-ROM ...

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Wait function in slave mode (I A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. Three interrupt sources Data transfer end ...

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Formatless dedicated clock (channel 0 only) ø PS SCL Noise canceler SDA Noise canceler Legend: 2 ICCR bus control register 2 ICMR bus mode register 2 ICSR bus status register 2 ICDR ...

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Vcc VCC SCL SCL in SCL out SDA SDA in SDA out (Master) This chip Figure 16.2 I 16.1.3 Input/Output Pins Table 16.1 summarizes the input/output pins used by the I 2 Table 16 Bus Interface Pins Channel ...

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Register Configuration Table 16.2 summarizes the registers of the I Table 16.2 Register Configuration Channel Name bus control register bus status register bus data register bus ...

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Register Descriptions 2 16.2 Bus Data Register (ICDR) Bit 7 ICDR7 Initial value — Read/Write R/W ICDRR Bit 7 ICDRR7 ICDRR6 Initial value — Read/Write R ICDRS Bit 7 ICDRS7 ICDRS6 Initial value — Read/Write — ICDRT ...

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ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS ...

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TDRE Description 0 The next transmit data is in ICDR (ICDRT), or transmission cannot be started [Clearing conditions] When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) When a stop condition is detected in the ...

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Slave Address Register (SAR) Bit 7 SVA6 Initial value 0 Read/Write R/W SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format ...

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DDCSWR SAR SARX Bit 6 Bit 0 Bit FSX Note not set this mode when automatic switching to the ...

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Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in DDCSWR to select the communication format bus format: addressing format with acknowledge bit Synchronous serial format: non-addressing format without ...

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Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master mode with the I the fall of the clock for the final data bit, the IRIC flag is ...

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Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel 1) or IICX0 (channel 0) bit in the STCR register, select the serial clock frequency in master mode. They should be set according to ...

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Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX ...

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Bit 7—I C Bus Interface Enable (ICE): Selects whether or not the I used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is cleared to ...

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Bit 5 Bit 4 MST TRS Operating Mode 0 0 Slave receive mode 1 Slave transmit mode 1 0 Master receive mode 1 Master transmit mode Bit 5 MST Description 0 Slave mode [Clearing conditions] 1. When 0 is written ...

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Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the acknowledge bit returned from the receiving device when using the I and continuous transfer is performed, or transfer aborted and error handling, etc., performed if ...

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Bit 2 BBSY Description 0 Bus is free [Clearing condition] When a stop condition is detected 1 Bus is busy [Setting condition] When a start condition is detected 2 Bit 1—I C Bus Interface Interrupt Request Flag (IRIC): Indicates that ...

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Bit 1 IRIC Description 0 Waiting for transfer, or transfer in progress [Clearing conditions] 1. When 0 is written in IRIC after reading IRIC = 1 2. When ICDR is written or read by the DTC (When the TDRE or ...

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When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a ...

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Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. ...

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Bit 7 ESTP Description 0 No error stop condition [Clearing conditions] 1. When 0 is written in ESTP after reading ESTP = 1 2. When the IRIC flag is cleared bus format slave ...

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Bit 5 IRTR Description 0 Waiting for transfer, or transfer in progress [Clearing conditions] 1. When 0 is written in IRTR after reading IRTR = 1 2. When the IRIC flag is cleared Continuous transfer state [Setting ...

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AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. ...

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Bit 1—General Call Address Recognition Flag (ADZ this flag is set the first frame following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set ...

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Serial/Timer Control Register (STCR) Bit 7 — Initial value 0 Read/Write R/W STCR is an 8-bit readable/writable register that controls register access, the I mode (when the on-chip IIC option is included), and on-chip flash memory (F-ZTAT versions), and ...

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DDC Switch Register (DDCSWR) Bit 7 SWE Initial value 0 Read/Write R/W Notes: *1 Only 0 can be written, to clear the flag. *2 Always read as 1. DDCSWR is an 8-bit readable/writable register that is used to initialize ...

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Bits 5—DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to the CPU when automatic format switching is executed for IIC channel 0. Bit 5 IE Description 0 Interrupt when automatic format switching is executed is ...

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Bit 3 Bit 2 Bit 1 CLR3 CLR2 CLR1 0 0 — — — 16.2.9 Module Stop Control Register (MSTPCR) Bit MSTP15 MSTP14 MSTP13 Initial value Read/Write R/W R/W R/W ...

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MSTPCRL Bit 3—Module Stop (MSTP3): Specifies IIC channel 1 module stop mode. MSTPCRL Bit 3 MSTP3 Description 0 IIC channel 1 module stop mode is cleared 1 IIC channel 1 module stop mode is set 16.3 Operation 2 16.3.1 I ...

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I C bus format ( FSX = 0) S SLA R ( bus format (start condition retransmission FSX = 0) S SLA ...

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Table 16 Bus Data Format Symbols Legend S Start condition. The master device drives SDA from high to low while SCL is high SLA Slave address, by which the master device selects a slave device R/W Indicates ...

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The master device sequentially sends the transmit clock and the data written to ICDR with the timing shown in figure 16.7. The selected slave device (i.e. , the slave device with the matching slave address) drives SDA low at the ...

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Start condition generation SCL (master output) SDA (master output) SDA [5] (slave output) IRIC IRTR ICDR Note: Data write timing in ICDR ICDR Writing enable ICDR Writing prohibited User processing [4] Write BBSY = 1 and SCP = 0 (start ...

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The IRIC flag is set the fall of the 8th clock of a one-frame reception clock. At this point, if the IEIC bit of ICCR is set interrupt request is generated to the ...

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Master transmit mode Master receive mode SCL 9 1 (master output) SDA A Bit7 (slave output) SDA (master output) IRIC IRTR ICDR User processing [1] TRS cleared to 0 [2] ICDR read WAIT set to 1 ACKB cleared to 0 ...

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Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. [1] Set ...

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Start condition generation SCL 1 (master output) SCL (slave output) SDA Bit 7 (master output) SDA (slave output) RDRF IRIC ICDRS ICDRR User processing Figure 16.9 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) 38 ...

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SCL 7 8 (master output) SCL (slave output) SDA Bit 1 Bit 0 (master output) Data 1 SDA (slave output) RDRF IRIC ICDRS ICDRR User processing Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = ...

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After clearing the IRIC flag to 0, write the next data to ICDR. The slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at ...

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IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF ...

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Automatic Switching from Formatless Mode to I Setting the SW bit DDCSWR enables formatless mode to be selected as the IIC0 operating mode. Switching from formatless mode to the I automatically when a falling edge is ...

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Operation Using the DTC 2 The I C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of ...

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Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches ...

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Start Initialize Read BBSY in ICCR No BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR Write BBSY = 1 and SCP = 0 in ICCR Read IRIC in ICCR No IRIC = 1? Yes ...

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Master receive operation Set TRS = 0 in ICCR Set WAIT = 1 in ICMR Set ACKB = 0 in ICSR Clear IRIC in ICCR Read IRIC in ICCR No Clear IRIC in ICCR Read IRIC in ICCR No Clear ...

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Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC in ICCR No IRIC = 1? Yes Read AAS and ADZ in ICSR No AAS = 1 and ADZ = ...

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Slave transmit mode Clear IRIC in ICCR Write transmit data in ICDR Clear IRIC in ICCR Read IRIC in ICCR No IRIC = 1? Yes Read ACKB in ICSR End No of transmission (ACKB = 1)? Yes Set TRS = ...

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Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR) Internal latches used to retain ...

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Usage Notes In master mode instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing ...

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The I C bus interface specification for the SCL rise time t speed mode). In master mode, the I one bit at a time during communication the time determined by the input clock of the I extended. ...

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Table 16 Bus Timing (with Maximum Influence cyc Item Indication t 0.5t Standard SCLHO SCLO (–t ) mode Sr High-speed mode t 0.5t Standard SCLLO SCLO (–t ) mode Sf High-speed mode t 0.5t ...

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Item Indication t 3t Standard SDAHO cyc mode High-speed mode Notes: *1 Does not meet the I is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up ...

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SDA Bit 0 SCL 8 Internal clock BBSY bit Master receive mode Figure 16.18 Points for Attention Concerning Reading of Master Receive Data Notes on Start Condition Issuance for Retransmission Figure 16-19 shows the timing of start condition issuance for ...

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No IRIC Yes Clear IRIC in ICSR No Start condition Other processing issuance? Yes Read SCL pin No SCL= Low ? Yes Write BBSY = 1, SCP = 0 (ICSR) No IRIC Yes Write transmit data ...

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Notes Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance is large there is a slave device of the type ...

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Section 22 Electrical Characteristics 22.1 Voltage of Power Supply and Operating Range The power supply voltage and operating range (shaded part) for each product are shown in table 22.1. Table 22.1 Power Supply Voltage and Operating Range (1) Product/ Power ...

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Table 22.1 Power Supply Voltage and Operating Range (2) Product/ Power supply 5 V version V HD6432128S CC 5.5 V HD6432128SW HD6432127S 4.5 V HD6432127SW 2 MHz fop VCC1 pin V = 5.0 V ± 10% CC VCL pin V ...

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Electrical Characteristics [H8S/2128 Series, H8S/2128 F-ZTAT] 22.2.1 Absolute Maximum Ratings Table 22.2 lists the absolute maximum ratings. Table 22.2 Absolute Maximum Ratings Item Power supply voltage Input voltage (except ports 6, and 7) Input voltage (CIN input not selected ...

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DC Characteristics Table 22.3 lists the DC characteristics. Table 22.4 lists the permissible output currents. Table 22.3 DC Characteristics (1) Conditions 5.0 V ± 10 –20 to +75° –40 to ...

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Item Three-state Ports leakage current (off state) Input Ports pull-up MOS current RES Input capacitance NMI P52, P47, P24, P23 Input pins except (4) above Current Normal operation 6 dissipation * Sleep mode Standby ...

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The upper limit of the port 6 applied voltage is V selected, and the lower of V When a pin is in output mode, the output voltage is equivalent to the applied voltage. *6 Current dissipation values are for ...

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Table 22.3 DC Characteristics ( Conditions –20 to +75° –40 to +85° Item 2 5 P67 to P60 * * Schmitt trigger input ...

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Item Three-state Ports leakage current (off state) Input Ports pull-up MOS current RES Input capacitance NMI P52, P47, P24, P23 Input pins except (4) above Current Normal operation 6 dissipation * Sleep mode Standby ...

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Current dissipation values are for V output pins unloaded and the on-chip pull-up MOSs in the off state. *7 The values are for V RAM *8 For flash memory program/erase operations, the applicable ranges are V 5.5 V and ...

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Table 22.3 DC Characteristics (3) Conditions (Mask ROM version): V (Flash memory version): V Item 2 5 P67 to P60 * * Schmitt trigger input IRQ2 to IRQ0 * voltage RES, STBY, Input high voltage NMI, MD1, MD0 EXTAL Port ...

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Item Three-state Ports leakage current (off state) Input Ports pull-up MOS current RES Input capacitance NMI P52, P47, P24, P23 Input pins except (4) above Current Normal operation 6 dissipation * Sleep mode Standby ...

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The upper limit of the port 6 applied voltage is V selected, and the lower of V When a pin is in output mode, the output voltage is equivalent to the applied voltage. *6 Current dissipation values are for ...

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Table 22.4 Permissible Output Currents Conditions 4 5 –40 to +85°C (wide-range specifications) Item Permissible output SCL1, SCL0, SDA1, low current (per pin) SDA0 Ports Other output pins ...

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Table 22.5 Bus Drive Characteristics Conditions 2 5 Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Symbol – Schmitt trigger V T input voltage + – ...

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Figure 22.2 LED Drive Circuit (Example) 22.2.3 AC Characteristics Figure 22.3 shows the test conditions for the AC characteristics. Chip output pin C This chip Ports LED Figure 22.3 Output Load Circuit ...

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Clock Timing Table 22.6 shows the clock timing. The clock timing specified here covers clock (ø) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin ...

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Figure 22.4 System Clock Timing EXTAL t DEXT V CC STBY t OSC1 RES ø Figure 22.5 Oscillation Settling Timing ø NMI IRQi ( Figure 22.6 Oscillation Setting Timing (Exiting Software Standby Mode) t cyc ...

Page 82

Control Signal Timing Table 22.7 shows the control signal timing. The only external interrupts that can operate on the subclock (ø = 32.768 kHz) are NMI and IRQ0, 1, and IRQ2. Table 22.7 Control Signal Timing Condition A: V ...

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RES Figure 22.7 Reset Input Timing ø NMI IRQi ( IRQ Edge input IRQ Level input Figure 22.8 Interrupt Input Timing t t RESS RESS t RESW t t NMIS NMIH t NMIW t IRQW ...

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Bus Timing Table 22.8 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (ø = 32.768 kHz). Table 22.8 Bus Timing Condition 5.0 V ± 10 ...

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Condition A Item Symbol Min Read data t — ACC3 access time 3 Read data t — ACC4 access time 4 Read data t — ACC5 access time 5 WR delay t — WRD1 time 1 WR delay t — ...

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A15 to A0, IOS* AS* RD (read (read) WR (write (write) Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.9 Basic ...

Page 87

T ø A15 to A0, IOS CSD AS (read (read) WR (write (write) Note and IOS are the same pin. The function is selected ...

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T 1 ø A15 to A0, IOS* AS* RD (read (read) WR (write (write) WAIT Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. ...

Page 89

T 1 ø A15 to A0, IOS* AS* RD (read (read) Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.12 Burst ROM Access Timing (Two-State ...

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A15 to A0, IOS* AS* RD (read (read) Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.13 Burst ROM Access Timing (One-State Access) 82 ...

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Timing of On-Chip Supporting Modules Tables 22.9 and 22.10 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (ø = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, ...

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Item TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer Single clock edge pulse Both width edges PWM, Pulse output PWMX delay time SCI Input Asynchro- clock nous cycle Synchro- nous Input clock ...

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Ports (read) Ports (write) Figure 22.14 I/O Port Input/Output Timing ø t FTOA, FTOB FTIA, FTIB, FTIC, FTID Figure 22.15 FRT Input/Output Timing ø FTCI t FTCWL Figure 22.16 FRT Clock Input Timing ...

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TMO0, TMO1 TMOX Figure 22.17 8-Bit Timer Output Timing ø TMCI0, TMCI1 TMIX, TMIY Figure 22.18 8-Bit Timer Clock Input Timing ø TMRI0, TMRI1 TMIX, TMIY Figure 22.19 8-Bit Timer Reset Input Timing ø PW15 to PW0, PWX1, PWX0 ...

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SCK0, SCK1 Figure 22.21 SCK Clock Input Timing SCK0, SCK1 TxD0, TxD1 (transmit data) RxD0, RxD1 (receive data) Figure 22.22 SCI Input/Output Timing (Synchronous Mode) ø ADTRG Figure 22.23 A/D Converter External Trigger Input Timing t t SCKW SCKr t ...

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Table 22. Bus Timing Conditions 2 5 –20 to +75°C a Item Symbol SCL clock cycle t SCL time SCL clock high t SCLH pulse width SCL clock ...

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V IH SDA0, SDA1 BUF t STAH SCL0, SCL1 SCLL t Sf Note and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 22.24 ...

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A/D Conversion Characteristics Tables 22.11 and 22.12 list the A/D conversion characteristics. Table 22.11 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition 5.0 V ± 10 ...

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Table 22.12 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition 5.0 V ± 10 ø MHz to maximum operating frequency –20 ...

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Flash Memory Characteristics Table 22.13 shows the flash memory characteristics. Table 22.13 Flash Memory Characteristics Conditions (5 V version Conditions for low-voltage version:V Item Programming time * * * Erase time ...

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Item Erase Wait time after SWE-bit setting * Wait time after ESU-bit setting * Wait time after 1 E-bit setting * Wait time after 1 E-bit clear * Wait time after ESU-bit clear * Wait time after EV-bit setting * ...

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Usage Note The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. However, actual performance figures, operating margins, noise margins, and other properties may vary due to ...

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Electrical Characteristics [H8S/2128S Series] 22.3.1 Absolute Maximum Ratings Table 22.14 lists the absolute maximum ratings. Table 22.14 Absolute Maximum Ratings Item 1 Power supply voltage * 1 Power supply voltage * (3 V version) 2 Power supply voltage * ...

Page 104

DC Characteristics Table 22.15 lists the DC characteristics. Table 22.16 lists the permissible output currents. Table 22.15 DC Characteristics (1) Conditions 5.0 V ± 10 –20 to +75°C (regular specifications ...

Page 105

Item Three-state Ports leakage current (off state) Input Ports pull-up MOS current RES Input capacitance NMI P52, P47, P24, P23 Input pins except (4) above Current Normal operation 6 dissipation * Sleep mode Standby ...

Page 106

The upper limit of the port 6 applied voltage is V selected, and the lower of V When a pin is in output mode, the output voltage is equivalent to the applied voltage. *6 Current dissipation values are for ...

Page 107

Table 22.15 DC Characteristics (2) Conditions 4 5 –20 to +75°C (regular specifications –40 to +85°C (wide-range specifications) a Item 2 5 P67 to P60 * * Schmitt ...

Page 108

Item RES Input leakage STBY, NMI, MD1, current MD0 Port 7 Three-state Ports leakage current (off state) Input Ports pull-up MOS current RES Input capacitance NMI P52, P47, P24, P23 Input pins except (4) ...

Page 109

An external pull-up resistor is necessary to provide high-level output from SCL0 and SDA0 (ICE = 1). In the H8S/2128S Series, P52/SCK0 and P47 (ICE = 0) high levels are driven by NMOS. *5 The upper limit of the port ...

Page 110

Table 22.15 DC Characteristics (3) Conditions (Mask ROM version): V Item 2 5 P67 to P60 * * Schmitt trigger input IRQ2 to IRQ0 * voltage RES, STBY, Input high voltage NMI, MD1, MD0 EXTAL Port 7 Input pins except ...

Page 111

Item Three-state Ports leakage current (off state) Input Ports pull-up MOS current RES Input capacitance NMI P52, P47, P24, P23 Input pins except (4) above Current Normal operation 6 dissipation * Sleep mode Standby ...

Page 112

The upper limit of the port 6 applied voltage is V selected, and the lower of V When a pin is in output mode, the output voltage is equivalent to the applied voltage. *6 Current dissipation values are for ...

Page 113

Table 22.16 Permissible Output Currents Conditions 4 5 –40 to +85°C (wide-range specifications) Item Permissible output SCL1, SCL0, SDA1, low current (per pin) SDA0 Ports Other output pins ...

Page 114

Table 22.17 Bus Drive Characteristics Conditions 4 5 Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected) Item Symbol – Schmitt trigger V T input voltage + V T Input high voltage ...

Page 115

Figure 22.26 LED Drive Circuit (Example) 22.3.3 AC Characteristics Figure 22.3 shows the test conditions for the AC characteristics. Chip output pin C This chip Ports LED Figure 22.27 Output Load Circuit 600 ...

Page 116

Clock Timing Table 22.18 shows the clock timing. The clock timing specified here covers clock (ø) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin ...

Page 117

Figure 22.28 System Clock Timing EXTAL t DEXT V CC STBY t OSC1 RES ø Figure 22.29 Oscillation Settling Timing ø NMI IRQi ( Figure 22.30 Oscillation Setting Timing (Exiting Software Standby Mode) t cyc ...

Page 118

Control Signal Timing Table 22.19 shows the control signal timing. The only external interrupts that can operate on the subclock (ø = 32.768 kHz) are NMI and IRQ0, 1, and IRQ2. Table 22.19 Control Signal Timing Condition A: V ...

Page 119

RES Figure 22.31 Reset Input Timing ø NMI IRQi ( IRQ Edge input IRQ Level input Figure 22.32 Interrupt Input Timing t t RESS RESS t RESW t t NMIS NMIH t NMIW t IRQW ...

Page 120

Bus Timing Table 22.20 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (ø = 32.768 kHz). Table 22.20 Bus Timing Condition 5.0 V ± 10 ...

Page 121

Condition A Item Symbol Min Read data t — ACC3 access time 3 Read data t — ACC4 access time 4 Read data t — ACC5 access time 5 WR delay t — WRD1 time 1 WR delay t — ...

Page 122

A15 to A0, IOS* AS* RD (read (read) WR (write (write) Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.33 Basic ...

Page 123

T ø A15 to A0, IOS CSD AS (read (read) WR (write (write) Note and IOS are the same pin. The function is selected ...

Page 124

T 1 ø A15 to A0, IOS* AS* RD (read (read) WR (write (write) WAIT Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. ...

Page 125

T 1 ø A15 to A0, IOS* AS* RD (read (read) Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.36 Burst ROM Access Timing (Two-State ...

Page 126

A15 to A0, IOS* AS* RD (read (read) Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.37 Burst ROM Access Timing (One-State Access) 118 ...

Page 127

Timing of On-Chip Supporting Modules Tables 22.21 and 22.22 show the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (ø = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, ...

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Item TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer Single clock edge pulse Both width edges PWM, Pulse output PWMX delay time SCI Input Asynchro- clock nous cycle Synchro- nous Input clock ...

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Ports (read) Ports (write) Figure 22.38 I/O Port Input/Output Timing ø t FTOA, FTOB FTIA, FTIB, FTIC, FTID Figure 22.39 FRT Input/Output Timing ø FTCI t FTCWL Figure 22.40 FRT Clock Input Timing ...

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TMO0, TMO1 TMOX Figure 22.41 8-Bit Timer Output Timing ø TMCI0, TMCI1 TMIX, TMIY Figure 22.42 8-Bit Timer Clock Input Timing ø TMRI0, TMRI1 TMIX, TMIY Figure 22.43 8-Bit Timer Reset Input Timing ø PW15 to PW0, PWX1, PWX0 ...

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SCK0, SCK1 Figure 22.45 SCK Clock Input Timing SCK0, SCK1 TxD0, TxD1 (transmit data) RxD0, RxD1 (receive data) Figure 22.46 SCI Input/Output Timing (Synchronous Mode) ø ADTRG Figure 22.47 A/D Converter External Trigger Input Timing t t SCKW SCKr t ...

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Table 22. Bus Timing Conditions 4 5 maximum operating frequency, T Item Symbol SCL clock cycle t SCL time SCL clock high t SCLH pulse width SCL clock low t ...

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V IH SDA0, SDA1 BUF t STAH SCL0, SCL1 SCLL t Sf Note and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Retransmission start condition Figure 22.48 ...

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A/D Conversion Characteristics Tables 22.23 and 22.24 list the A/D conversion characteristics. Table 22.23 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition 5.0 V ± 10 ...

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Table 22.24 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition 5.0 V ± 10 ø MHz to maximum operating frequency –20 ...

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Usage Note (1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this manual. However, actual performance figures, operating margins, noise margins, and other properties may vary due ...

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Specification differences in internal I/O registers Mask ROM version of H8S/2128S, H8S/2127S are different from the H8S/2128 Series and H8S/2124 Series in the specification of control registers for peripheral functions. A/D converter: A/D Control Register (ADCR) H8S/2128 Series, Bit ...

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Electrical Characteristics [H8S/2124 Series] 22.4.1 Absolute Maximum Ratings Table 22.25 lists the absolute maximum ratings. Table 22.25 Absolute Maximum Ratings Item Power supply voltage Input voltage (except ports 6, and 7) Input voltage (CIN input not selected for port ...

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DC Characteristics Table 22.26 lists the DC characteristics. Table 22.27 lists the permissible output currents. Table 22.26 DC Characteristics (1) Conditions 5.0 V ± 10 –20 to +75°C (regular specifications ...

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Item Three-state Ports leakage current (off state) Input Ports pull-up MOS current RES Input capacitance NMI P52, P47, P24, P23 Input pins except (4) above Current Normal operation 5 dissipation * Sleep mode Standby ...

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Table 22.26 DC Characteristics (2) Conditions 4 5 –20 to +75°C (regular specifications –40 to +85°C (wide-range specifications) a Item 2 4 P67 to P60 * * Schmitt ...

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Item Three-state Ports leakage current (off state) Input Ports pull-up MOS current RES Input capacitance NMI P52, P47, P24, P23 Input pins except (4) above Current Normal operation 5 dissipation * Sleep mode Standby ...

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Table 22.26 DC Characteristics (3) Conditions : Item 2 4 P67 to P60 * * Schmitt trigger input IRQ2 to IRQ0 * voltage RES, ...

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Item Three-state Ports leakage current (off state) Input Ports pull-up MOS current RES Input capacitance NMI P52, P47, P24, P23 Input pins except (4) above Current Normal operation 5 dissipation * Sleep mode Standby ...

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Table 22.27 Permissible Output Currents Conditions 4 5 –40 to +85°C (wide-range specifications) Item Permissible output Ports low current (per pin) Other output pins Permissible output Total of ...

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This chip Figure 22.50 Darlington Pair Drive Circuit (Example) Figure 22.51 LED Drive Circuit (Example) 22.4.3 AC Characteristics Figure 22.52 shows the test conditions for the AC characteristics. Chip output pin C 138 2 k Port This chip Ports 1 ...

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Clock Timing Table 22.28 shows the clock timing. The clock timing specified here covers clock (ø) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin ...

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EXTAL t DEXT V CC STBY t OSC1 RES ø Figure 22.54 Oscillation Settling Timing ø NMI IRQi ( Figure 22.55 Oscillation Setting Timing (Exiting Software Standby Mode) 140 t cyc ...

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Control Signal Timing Table 22.29 shows the control signal timing. The only external interrupts that can operate on the subclock (ø = 32.768 kHz) are NMI and IRQ0, 1, and IRQ2. Table 22.29 Control Signal Timing Condition A: V ...

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RES ø NMI IRQi ( IRQ Edge input IRQ Level input 142 t RESS t RESW Figure 22.56 Reset Input Timing t NMIS t NMIW t IRQW t IRQS t IRQS Figure 22.57 Interrupt Input ...

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Bus Timing Table 22.30 shows the bus timing. Operation in external expansion mode is not guaranteed when operating on the subclock (ø = 32.768 kHz). Table 22.30 Bus Timing Condition 5.0 V ± 10 ...

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Condition A Item Symbol Min Read data t — ACC3 access time 3 Read data t — ACC4 access time 4 Read data t — ACC5 access time 5 WR delay t — WRD1 time 1 WR delay t — ...

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AD A15 to A0, IOS* t CSD AS* RD (read (read) WR (write (write) Note and IOS are the same pin. The function is selected by the IOSE bit in ...

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AD A15 to A0, IOS* t CSD AS* RD (read (read) WR (write (write) Note and IOS are the same pin. The function is selected by the IOSE bit in ...

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T 1 ø A15 to A0, IOS* AS* RD (read (read) WR (write (write) WAIT Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. ...

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T 1 ø A15 to A0, IOS* AS* RD (read (read) Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.61 Burst ROM Access Timing (Two-State ...

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T 1 ø A15 to A0, IOS* AS* RD (read (read) Note and IOS are the same pin. The function is selected by the IOSE bit in SYSCR. Figure 22.62 Burst ROM Access Timing (One-State ...

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Timing of On-Chip Supporting Modules Table 22.31 shows the on-chip supporting module timing. The only on-chip supporting modules that can operate in subclock operation (ø = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, and ...

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Item Symbol Min TMR Timer output t delay time Timer reset input t setup time Timer clock input t setup time Timer Single t clock edge pulse Both t width edges SCI Input Asynchro- t clock nous cycle Synchro- nous ...

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Ports (read) Ports (write) Figure 22.63 I/O Port Input/Output Timing ø FTOA, FTOB FTIA, FTIB, FTIC, FTID Figure 22.64 FRT Input/Output Timing ø FTCI Figure 22.65 FRT Clock Input Timing 152 T T ...

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TMO0, TMO1 Figure 22.66 8-Bit Timer Output Timing ø TMCI0, TMCI1, TMIY Figure 22.67 8-Bit Timer Clock Input Timing ø TMRI0, TMRI1, TMIY Figure 22.68 8-Bit Timer Reset Input Timing SCK0, SCK1 Figure 22.69 SCK Clock Input Timing t ...

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SCK0, SCK1 TxD0, TxD1 (transmit data) RxD0, RxD1 (receive data) Figure 22.70 SCI Input/Output Timing (Synchronous Mode) ø ADTRG Figure 22.71 A/D Converter External Trigger Input Timing 154 t TXD t t RXS RXH t TRGS ...

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A/D Conversion Characteristics Tables 22.32 and 22.33 list the A/D conversion characteristics. Table 22.32 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition 5.0 V ± 10 ...

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Table 22.33 A/D Conversion Characteristics (CIN7 to CIN0 Input: 134/266-State Conversion) Condition 5.0 V ± 10 ø MHz to maximum operating frequency –20 ...

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Usage Note The specifications of the H8S/2128 F-ZTAT version and H8S/2124 Series mask ROM version differ in terms of on-chip module functions provided and port (P47, P52) output specifications. Also, while the F-ZTAT and mask ROM versions both satisfy ...

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158 ...

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Appendix F Product Code Lineup Table F.1 H8S/2128 Series and H8S/2124 Series Product Code Lineup — Preliminary — Product Type H8S/2128 H8S/2128 F-ZTAT Series version H8S/2127 Mask ROM version H8S/2126 Mask ROM version Product Code Standard product HD64F2128 (5 V/4 ...

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Product Type H8S/2128S H8S/2128S Mask ROM Series version H8S/2127S Mask ROM version 160 Product Code Standard product HD6432128S (5 V version version) Low-voltage version HD6432128SV (3 V version) Standard product HD6432128SW HD6432128SW(***)PS 64-pin shrink 2 with on-chip I ...

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Product Type H8S/2124 H8S/2122 Mask ROM Series version H8S/2120 Mask ROM version Note: (***) is the ROM code. The F-ZTAT version of the H8S/2128 has an on-chip I The F-ZTAT 5 V/4 V version supports the operating ranges of the ...

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162 ...

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H8S/2128 Series, H8S/2124 Series, H8S/2128F-ZTAT™ Hardware Manual (Supplement) Publication Date: 1st Edition, December 1997 3rd Edition, May 2002 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright ...

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