RS8228EBG Conexant Systems, Inc., RS8228EBG Datasheet

no-image

RS8228EBG

Manufacturer Part Number
RS8228EBG
Description
Octal ATM Transmission Convergence PHY Device
Manufacturer
Conexant Systems, Inc.
Datasheet

Specifications of RS8228EBG

Case
QFP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
RS8228EBG
Manufacturer:
CONEXANT
Quantity:
1 831
Part Number:
RS8228EBG
Manufacturer:
CONEXANT/PBF
Quantity:
677
Part Number:
RS8228EBG
Manufacturer:
CONEXANT
Quantity:
2 651
R O C K W E L L
S E M I C O N D U C T O R
S Y S T E M S
Network
access
RS8228
Octal ATM Transmission
Convergence PHY Device
datasheett
P R O V I D I N G
H I G H
S P E E D
M U L T I M E D I A
C O N N E C T I O N S
September 1998

Related parts for RS8228EBG

RS8228EBG Summary of contents

Page 1

Network access ...

Page 2

Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. RS8228 Octal ATM Transmission Convergence PHY Device The RS8228 Octal ATM Transmission Convergence PHY device dramatically improves performance ...

Page 3

... Manufacturing Model Number RS8228EBG Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved. Print date: September 1998 Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is assumed for its use ...

Page 4

Framer (Line) Interface Section • Programmable bit or byte synchronous serial interface • Direct connection to external Rockwell components for: – T1/E1 – DS3 – E3 – J2 – xDSL – General purpose mode • Interrupt and chip select signals ...

Page 5

...

Page 6

Table of Contents List of Figures ...

Page 7

Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 8

Octal ATM Transmission Convergence PHY Device 0x23—RXIDL4 (Receive Idle Cell Header Control Register ...

Page 9

Appendix B: Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 10

List of Figures Figure 1-1. RS8228 Connected to a RS8398 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11

List of Figures x Octal ATM Transmission Convergence PHY Device Advance N8228DSA RS8228 ...

Page 12

List of Tables Table 1-1. RS8228 Pin Descriptions ...

Page 13

List of Tables xii Octal ATM Transmission Convergence PHY Device Advance N8228DSA RS8228 ...

Page 14

Product Description The RS8228 Octal ATM Transmission Convergence (TC) PHY device dramati- cally increases the level of integration for switches and access systems. The RS8228 integrates all of the ATM Layer processing functions found in the ATM Forum Cell ...

Page 15

Product Description 1.1 Application Overview 1.1 Application Overview The RS8228 is typically used with line framer devices like the RS8398 T1/E1 octal transceiver, the Bt8970 zip-wire MODEM or the Bt8953 HDLC framer. It provides a chip-select feature that allows ...

Page 16

RS8228 Octal ATM Transmission Convergence PHY Device 1.2 Logic Diagram Figure 1 logic diagram of the RS8228’s functional modules. Pin descrip- tions are given in Table 1-1. Figure 1-2. RS8228 Logic Diagram Reset I One Second Input I ...

Page 17

Product Description 1.3 Pin Diagram and Definitions 1.3 Pin Diagram and Definitions Figure 1 pinout diagram for the RS8228 single CMOS integrated cir- cuit packaged in a 272-pin BGA. All unused input pins should ...

Page 18

RS8228 Octal ATM Transmission Convergence PHY Device Figure 1-3. RS8228 Pinout Diagram (top view LStatOut[2][4] LRxData[5] LStatOut[0][ GND LTxMrk[5] LStatOut[3][5] 1 LStatOut[1][4] LTxData[5] LStatOut[2][ LStatOut[3][4] LStatOut[0][4] LRxMrk[5] LRxHld[4] ...

Page 19

Product Description 1.3 Pin Diagram and Definitions Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name Reset~ Device Reset OneSecIn One-Second Input OneSecOut One-Second Output 8kHzIn One-Second Refer- ence Clock Input 6 Octal ATM Transmission Convergence PHY Device Driver ...

Page 20

RS8228 Octal ATM Transmission Convergence PHY Device Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name LTxClk[0] Line Transmit Clock LTxClk[1] Input (ports 0-7) LTxClk[2] LTxClk[3] LTxClk[4] LTxClk[5] LTxClk[6] LTxClk[7] LTxData[0] Line Transmit Data LTxData[1] Output (ports 0-7) LTxData[2] LTxData[3] ...

Page 21

Product Description 1.3 Pin Diagram and Definitions Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name LRxMrk[0] Line Receive Data LRxMrk[1] Marker (ports 0-7) LRxMrk[2] LRxMrk[3] LRxMrk[4] LRxMrk[5] LRxMrk[6] LRxMrk[7] LRxHld[0] Line Receiver Hold LRxHld[1] Input (ports 0-7) LRxHld[2] ...

Page 22

RS8228 Octal ATM Transmission Convergence PHY Device Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name LStatOut[2][0] Line Status Output 2 LStatOut[2][1] (ports 0-7) LStatOut[2][2] LStatOut[2][3] LStatOut[2][4] LStatOut[2][5] LStatOut[2][6] LStatOut[2][7] LStatOut[1][0] Line Status Output 1 LStatOut[1][1] (ports 0-7) LStatOut[1][2] LStatOut[1][3] ...

Page 23

Product Description 1.3 Pin Diagram and Definitions Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name MClk Microprocessor Clock MSyncMode Microprocessor Syn- chronous/Asynchro- nous Bus Mode Select MCs~ Microprocessor Chip Select 10 Octal ATM Transmission Convergence PHY Device Driver ...

Page 24

RS8228 Octal ATM Transmission Convergence PHY Device Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name MW/R~ Microprocessor Write/Read or or MRd~ Read Control MAs~ Microprocessor Address Strobe or or MWr~ Write Control Driver No. Type I/O Strength P17 TTL ...

Page 25

Product Description 1.3 Pin Diagram and Definitions Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name MAddr[12] Microprocessor Address Bus MAddr[11] MAddr[10] MAddr[9] MAddr[8] MAddr[7] MAddr[6] MAddr[5] MAddr[4] MAddr[3] MAddr[2] MAddr[1] MAddr[0] MData[7] Microprocessor Data Bus MData[6] MData[5] MData[4] ...

Page 26

RS8228 Octal ATM Transmission Convergence PHY Device Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name TRST~ Test Reset TCK Test Clock TMS Test Mode Select TDI Test Data Input TDO Test Data Output UTxClk UTOPIA Transmit Clock UTxEnb~ Transmit ...

Page 27

Product Description 1.3 Pin Diagram and Definitions Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name UTxData[0] LSB UTxData[1] UTxData[2] UTxData[3] UTOPIA Transmit Data UTxData[4] UTxData[5] UTxData[6] UTxData[7] UTxData[8] UTxData[9] UTxData[10] UTxData[11] UTxData[12] UTxData[13] UTxData[14] UTxData[15] MSB UTxPrty UTOPIA ...

Page 28

RS8228 Octal ATM Transmission Convergence PHY Device Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name URxClk UTOPIA Receive Clock URxEnb~ Receive Enable URxAddr[0] LSB URxAddr[1] URxAddr[2] UTOPIA Receive Address URxAddr[3] URxAddr[4] MSB Driver No. Type I/O Strength V13 TTL ...

Page 29

Product Description 1.3 Pin Diagram and Definitions Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name URxData[0] LSB URxData[1] URxData[2] URxData[3] UTOPIA Receive Data Bus URxData[4] URxData[5] URxData[6] URxData[7] URxData[8] URxData[9] URxData[10] URxData[11] URxData[12] URxData[13] URxData[14] URxData[15] MSB URxPrty ...

Page 30

RS8228 Octal ATM Transmission Convergence PHY Device Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name PWR Supply Voltage GND Ground VGG Electrostatic Dis- charge (ESD) Supply Voltage Driver No. Type I/O Strength D6 – – These pins are power ...

Page 31

Product Description 1.3 Pin Diagram and Definitions Table 1-1. RS8228 Pin Descriptions Pin Label Signal Name Test 1 Manufacturing Test 1 Test 2 Manufacturing Test 2 Test 3 Manufacturing Test 3 All input and bi-directional pins have hysteresis. NOTE: ...

Page 32

RS8228 Octal ATM Transmission Convergence PHY Device 1.4 Block Diagram and Descriptions Figure 1 detailed block diagram of the Peak 8 device. Traffic is transmitted from the ATM layer device, via the UTOPIA bus, in either an 8 ...

Page 33

Product Description 1.4 Block Diagram and Descriptions 20 Octal ATM Transmission Convergence PHY Device N8228DSA Advance RS8228 ...

Page 34

Functional Description This chapter describes the primary functions of the RS8228, including the ATM cell processor, the UTOPIA interface, and the microprocessor interface. 2.1 ATM Cell Processor The RS8228’s ATM cell receiver block is responsible for recovering cell align- ...

Page 35

Functional Description 2.1 ATM Cell Processor In normal operation, the 4-octet header field in the outgoing cell is passed on from the ATM layer device. Header patterns can be modified in the TXHDR1-4 registers (0x10-13) and inserted into outgoing ...

Page 36

RS8228 Octal ATM Transmission Convergence PHY Device 2.1.2 ATM Cell Receiver The ATM cell receiver performs cell delineation on incoming data cells by searching for the position of a valid HEC field within the cell. The HEC coset can be ...

Page 37

Functional Description 2.1 ATM Cell Processor in the data stream that meet the cell delineation criteria are valid headers (or just the HEC bytes in DSS). Figure 2-2. Header Error Check Process Errors Detected (Drop Cell) Detection Mode Apparent ...

Page 38

RS8228 Octal ATM Transmission Convergence PHY Device Table 2-1. Cell Screening - Matching Receive Cell Mask Bit Table 2-2. Cell Screening - Accept/Reject Cell 2.1.3 Cell Scrambler The ATM standard requires cell scrambling in order to ensure that only valid ...

Page 39

Functional Description 2.2 Framing Modes 2.2 Framing Modes The RS8228’s eight ports can be individually configured for the major framing modes Mbps; T1/E1, DS3, E3/G.832 and J2. Two general purpose fram- ing modes provide an interface ...

Page 40

RS8228 Octal ATM Transmission Convergence PHY Device Figure 2-3. Bt8370 Interface Diagram 2048/1536k clock TX Frame Marker TS31/24 Tx Serial Data LSB 0 E1 Mod Count 0 T1 Mod Count Rx Frame Marker TS31/24 Rx Serial Data LSB 0 E1 ...

Page 41

Functional Description 2.2 Framing Modes 2.2.2 DS3 Interface The RS8228 interfaces directly to the Bt8330 DS3 framer as shown in Figure 2-4. The RS8228 receives a DS3 data stream from the external framer, extracts the ATM cells, ignores the ...

Page 42

RS8228 Octal ATM Transmission Convergence PHY Device 2.2.3 E3/G.832 34.368 Mbps Interface The RS8228 interfaces directly to the a E3 framer as shown in Figure 2-5. The RS8228 receives a data stream from the external framer, extracts the ATM cells, ...

Page 43

Functional Description 2.2 Framing Modes 2.2.4 J2 6.312 Mbps Interface The RS8228 interfaces directly to the a J2 framer as shown in Figure 2-6. The RS8228 receives a data stream from the external framer, extracts the ATM cells, ignores ...

Page 44

RS8228 Octal ATM Transmission Convergence PHY Device 2.2.5 General Purpose Mode Interface with Frame Synchronization The RS8228 has a general purpose mode interface as shown in Figure 2-7. The RS8228 receives a data stream from the external framer, extracts the ...

Page 45

Functional Description 2.2 Framing Modes 2.2.6 General Purpose Mode Interface without Frame Synchronization The RS8228 has a general purpose mode interface as shown in Figure 2-8. This mode allows connection with framers that do not provide frame synchronization. The ...

Page 46

RS8228 Octal ATM Transmission Convergence PHY Device 2.3 UTOPIA Interface The RS8228 uses the ATM Forum’s UTOPIA interface as its host interface to communicate with the ATM layer device. This interface is UTOPIA Level 2 com- pliant and UTOPIA Level ...

Page 47

Functional Description 2.3 UTOPIA Interface In 16-bit mode, the cells consists of 54 bytes as shown in Table 2-4. The first five bytes contain header information. The sixth byte, UDF2, is required to main- tain alignment but is not ...

Page 48

RS8228 Octal ATM Transmission Convergence PHY Device This error can be observed either in the ParErr bit (bit 7) in the TXCELL register (0x2E the ParErrInt bit (bit 7) in the TXCELLINT register (0x2C). Systems that do not ...

Page 49

Functional Description 2.4 Microprocessor Interface reserved for the null address. The UTOPIA address should be changed only when the device or port is in the reset state. UTOPIA bus conflicts can occur if different RS8228 ports are programmed with ...

Page 50

RS8228 Octal ATM Transmission Convergence PHY Device a reset state while the control registers are being programmed. When the reset bit is deasserted, all changes to the registers take place simultaneously. At the device level, the software-controlled DevMstRst, bit 7, ...

Page 51

Functional Description 2.4 Microprocessor Interface 2.4.4 One-second Latching The RS8228’s implementation of one-second latching assures the integrity of the statistics being gathered by the network management software. Internal statistics counters can be latched at one-second intervals, which are synchronized ...

Page 52

RS8228 Octal ATM Transmission Convergence PHY Device Table 2-6. Chip Selects 1000-11FF 1200 - 13FF 1400 - 15FF 1600 - 17FF 1800 - 19FF 1A00 - 1BFF 1C00 - 1DFF 1E00 - 1FFF 2.4.6 Interrupts The RS8228’s interrupt indications can ...

Page 53

Functional Description 2.4 Microprocessor Interface Figure 2 flow chart of the interrupt generation process. Figure 2-9. Interrupt Indication Flow Chart OneSecInt or ExInt Event Occurs Figure 2-10 shows the registers involved in the interrupt generation process. 40 ...

Page 54

RS8228 Octal ATM Transmission Convergence PHY Device Figure 2-10. Interrupt Indication Diagram TXCELLINT (0x01EC) ParErrInt 7 SOCErrInt 6 XmtOvflInt 5 RcvOvflInt 4 OR CellSentInt 3 2 BusCnflctInt 1 Reserved 0 Reserved Outputs Enabled by ENCELLT (0x01E8) RXCELLINT (0x01ED) LOCDInt 7 ...

Page 55

Functional Description 2.4 Microprocessor Interface 2.4.6.2 Interrupt When an interrupt occurs on the MInt~ pin (pin B19), it could have been gener- Servicing ated by any of 128 events. The RS8228’s interrupt indication process ensures that a maximum of ...

Page 56

RS8228 Octal ATM Transmission Convergence PHY Device 2.5 Source Loopback Source loopback checks that the host (the ATM layer) is communicating with the PHY enabled and disabled in bit 5 the PMODE register (0x04). When source loopback is ...

Page 57

Functional Description 2.5 Source Loopback 44 Octal ATM Transmission Convergence PHY Device Advance N8228DSA RS8228 ...

Page 58

Registers The RS8228 registers are used to control and observe the device’s operations. Table 3-1 provides a list of the address ranges. There is a device control and status range along with eight port ranges and eight framer ranges. ...

Page 59

Registers The device level registers in Table 3-2 provide control for the device’s major operating modes as well as sta- tus and control for summary interrupts. Table 3-2. Device Control and Status Registers Address Name Type 0x0200 SUMPORT R ...

Page 60

RS8228 Octal ATM Transmission Convergence PHY Device Table 3-3. Port Control and Status Registers ( Port Offset Name Type Address 0x0F — — 0x10 TXHDR1 R/W 0x11 TXHDR2 R/W 0x12 TXHDR3 R/W 0x13 TXHDR4 R/W 0x14 TXIDL1 R/W ...

Page 61

Registers Table 3-3. Port Control and Status Registers ( Port Offset Name Type Address 0x2C TXCELLINT R 0x2D RXCELLINT R 0x2E TXCELL R 0x2F RXCELL R 0x30 LOCDCNT R 0x31 CORRCNT R 0x32 UNCCNT R 0x33 — ...

Page 62

RS8228 Octal ATM Transmission Convergence PHY Device 3.1 General Use Registers This section describes several registers that are used for RS8228’s basic functions, including device-level and port-level operating modes. 0x0202—MODE (Device Mode Control Register) The MODE register controls the device-level ...

Page 63

Registers 3.1 General Use Registers 0x04—PMODE (Port Mode Control Register) The PMODE register controls the port-level software resets, source loopback, and physical layer interface mode. Bit Default Name 7 0 PrtMstRst 6 0 PrtLgcRst SrcLoop 4 ...

Page 64

RS8228 Octal ATM Transmission Convergence PHY Device 0x05—IOMODE (Input/Output Mode Control Register) The IOMODE register controls the line interface signal polarities and status outputs. Bit Default Name RxHldPol RxMrkPol 5 0 RxClkPol 4 0 ...

Page 65

Registers 3.1 General Use Registers 0x07—OUTSTAT (Output Pin Control Register) The OUTSTAT register contains the values that will be reflected on the LStatOut[3:0] pins when StatSel[1:0] (bits 1 and 0) in the IOMODE register (0x05), is written to a ...

Page 66

RS8228 Octal ATM Transmission Convergence PHY Device 3.2 Cell Transmit Registers This section describes the control registers used for transmission of traffic. 0x08—CGEN (Cell Generation Control Register) The CGEN register controls the device’s cell generation functions. Bit Default Name 7 ...

Page 67

Registers 3.2 Cell Transmit Registers 0x09—HDRFIELD (Header Field Control Register) The HDRFIELD register controls the header insertion elements. Bit Default Name 7 0 — — — InsGFC 3 0 InsVPI 2 0 InsVCI ...

Page 68

RS8228 Octal ATM Transmission Convergence PHY Device 0x0B—ERRPAT (Error Pattern Control Register) The ERRPAT register provides the error pattern for the HEC error insertion function. ErrHEC (bit 4) in the CGEN register (0x08) enables this function. Each bit in the ...

Page 69

Registers 3.2 Cell Transmit Registers 0x11—TXHDR2 (Transmit Cell Header Control Register 2) The TXHDR2 register contains the second byte of the Transmit Cell Header. (See 0x10—TXHDR1.) Bit Default Name 7 0 TxHdr2[ TxHdr2[ TxHdr2[5] 4 ...

Page 70

RS8228 Octal ATM Transmission Convergence PHY Device 0x13—TXHDR4 (Transmit Cell Header Control Register 4) The TXHDR4 register contains the fourth byte of the Transmit Cell Header. (See 0x10—TXHDR1.) Bit Default Name 7 0 TxHdr4[ TxHdr4[ TxHdr4[5] ...

Page 71

Registers 3.2 Cell Transmit Registers 0x15—TXIDL2 (Transmit Idle Cell Header Control Register 2) The TXIDL2 register contains the second byte of the Transmit Idle Cell Header. (See 0x14—TXIDL1.) Bit Default Name 7 0 TxIdl2[ TxIdl2[ ...

Page 72

RS8228 Octal ATM Transmission Convergence PHY Device 0x17—TXIDL4 (Transmit Idle Cell Header Control Register 4) The TXIDL4 register contains the fourth byte of the Transmit Idle Cell Header. (See 0x14—TXIDL1.) Bit Default Name 7 0 TxIdl4[ TxIdl4[6] 5 ...

Page 73

Registers 3.3 Cell Receive Registers 3.3 Cell Receive Registers This section describes the control registers used for reception of traffic. 0x0C—CVAL (Cell Validation Control Register) The CVAL register controls the validation of incoming cells. Bit Default Name 7 0 ...

Page 74

RS8228 Octal ATM Transmission Convergence PHY Device 0x18—RXHDR1 (Receive Cell Header Control Register 1) The RXHDR1 register contains the first byte of the Receive Cell Header. The header values direct ATM cells to the UTOPIA port if an incoming ATM ...

Page 75

Registers 3.3 Cell Receive Registers 0x1A—RXHDR3 (Receive Cell Header Control Register 3) The RXHDR3 register contains the third byte of the Receive Cell Header. (See 0x18—RXHDR1.) Bit Default Name 7 0 RxHdr3[ RxHdr3[ RxHdr3[5] 4 ...

Page 76

RS8228 Octal ATM Transmission Convergence PHY Device 0x1C—RXMSK1 (Receive Cell Mask Control Register 1) The RXMSK1 register contains the first byte of the Receive Cell Mask. It modifies ATM cell screening, which compares the Receive Cell Header Registers to the ...

Page 77

Registers 3.3 Cell Receive Registers 0x1E—RXMSK3 (Receive Cell Mask Control Register 3) The RXMSK3 register contains the third byte of the Receive Cell Mask. (See 0x1D—RXMSK1.) Bit Default Name 7 1 RxMsk3[ RxMsk3[ RxMsk3[5] 4 ...

Page 78

RS8228 Octal ATM Transmission Convergence PHY Device 0x20—RXIDL1 (Receive Idle Cell Header Control Register 1) The RXIDL1 register contains the first byte of the Receive Idle Cell Header. It defines ATM idle cells for the cell receiver. Idle cells are ...

Page 79

Registers 3.3 Cell Receive Registers 0x22—RXIDL3 (Receive Idle Cell Header Control Register 3) The RXIDL3 register contains the third byte of the Receive Idle Cell Header. (See 0x20—RXIDL1.) Bit Default Name 7 0 RxIdl3[ RxIdl3[ ...

Page 80

RS8228 Octal ATM Transmission Convergence PHY Device 0x24—IDLMSK1 (Receive Idle Cell Mask Control Register 1) The IDLMSK1 register contains the first byte of the Receive Idle Cell Mask. It modifies ATM cell screening, which compares the Receive Idle Cell Header ...

Page 81

Registers 3.3 Cell Receive Registers 0x26—IDLMSK3 (Receive Idle Cell Mask Control Register 3) The IDLMSK3 register contains the third byte of the Receive Idle Cell Mask. (See 0x24—RXMSKL1.) Bit Default Name 7 0 IdlMsk3[ IdlMsk3[ ...

Page 82

RS8228 Octal ATM Transmission Convergence PHY Device 3.4 UTOPIA Registers This section describes the control registers for the UTOPIA operations. 0x0D—UTOP1 (UTOPIA Control Register 1) The UTOP1 register controls the UTOPIA resets, parity orientation, and the transmit FIFO fill-level threshold. ...

Page 83

Registers 3.4 UTOPIA Registers 0x0E—UTOP2 (UTOPIA Control Register 2) The UTOP2 register contains the multi-PHY address value for the device. Bit Default Name 7 0 Test Test UtopRxDis 4 0 MphyAddr[4] - ...

Page 84

RS8228 Octal ATM Transmission Convergence PHY Device 3.5 Status and Interrupt Registers These registers contain interrupt enables, interrupt indications, and status information. 0x0200—SUMPORT (Summary Port Interrupt Status Register) The SUMPORT register indicates the port summary interrupts. Bit Default Name 7 ...

Page 85

Registers 3.5 Status and Interrupt Registers 0x0201—ENSUMPORT (Summary Port Interrupt Control Register) The ENSUMPORT register controls which of the interrupts listed in the SUMPORT register (0x0200) are observed on the MInt~ (pin B19) if MInt~ is also enabled. See ...

Page 86

RS8228 Octal ATM Transmission Convergence PHY Device 0x01—ENSUMINT (Summary Interrupt Control Register) The ENSUMINT register controls which of the interrupts listed in the SUMINT register (0x00) appear in the SUMPORT register and on the MInt~ (pin B19), provided the corresponding ...

Page 87

Registers 3.5 Status and Interrupt Registers 0x29—ENCELLR (Receive Cell Interrupt Control Register) The ENCELLR register controls which of the interrupts listed in the RxCellInt register (0x2D) appear on the MInt~ pin (pin B19), provided that both EnRcvCellInt (bit 0) ...

Page 88

RS8228 Octal ATM Transmission Convergence PHY Device 0x2D—RXCELLINT (Receive Cell Interrupt Indication Status Register) The RXCELLINT register indicates that a change of status has occurred within the receive status signals. Bit Default Name LOCDInt ...

Page 89

Registers 3.5 Status and Interrupt Registers 0x2F—RXCELL (Receive Cell Status Register) The RXCELL register contains status for the cell receiver. Bit Default Name LOCD HECDet HECCorr RcvrHld ...

Page 90

RS8228 Octal ATM Transmission Convergence PHY Device 3.6 Counters This section describes the RS8228’s counters. When the counters fill, they saturate and do not rollover. The counts have been sized such that they will not saturate within a one-second interval. ...

Page 91

Registers 3.6 Counters 0x32—UNCCNT (Uncorrected HEC Error Counter) The UNCCNT counter tracks the number of uncorrected HEC errors. Bit Default Name 7 x UncCnt[ UncCnt[ UncCnt[ UncCnt[ UncCnt[ UncCnt[2] ...

Page 92

RS8228 Octal ATM Transmission Convergence PHY Device 0x35—TXCNTM (Transmitted Cell Counter [Mid Byte]) The TXCNTM counter tracks the number of transmitted cells. Bit Default Name 7 x TxCnt[15 TxCnt[14 TxCnt[13 TxCnt[12 TxCnt[11] ...

Page 93

Registers 3.6 Counters 0x38—RXCNTL (Received Cell Counter [Low Byte]) The RXCNTL counter tracks the number of received cells. This byte of the counter should be read first. Bit Default Name 7 x RxCnt[ RxCnt[ RxCnt[5] ...

Page 94

RS8228 Octal ATM Transmission Convergence PHY Device 0x3A—RXCNTH (Received Cell Counter [High Byte]) The RXCNTH counter tracks the number of received cells. Bit Default Name 7 0 — — — — — ...

Page 95

Registers 3.6 Counters 0x3D—NONCNTH (Non-matching Cell Counter [High Byte]) The NONCNTH counter tracks the number of non-matching cells. Bit Default Name 7 x NonCnt[15 NonCnt[14 NonCnt[13 NonCnt[12 NonCnt[11 NonCnt[10] ...

Page 96

Electrical and Mechanical Specifications This chapter describes the electrical and mechanical aspects of the RS8228. Included are timing diagrams, absolute maximum ratings, DC characteristics and mechanical drawings. 4.1 Timing Specifications This section provides timing diagrams and descriptions for the ...

Page 97

Electrical and Mechanical Specifications 4.1 Timing Specifications Table 4-1. Timing Diagram Nomenclature ( Symbol Timing Relationship t Pulse Width pw t Pulse Width High pwh t Pulse Width Low pwl t Setup Time s t Setup High ...

Page 98

RS8228 Octal ATM Transmission Convergence PHY Device Table 4-1. Timing Diagram Nomenclature ( Symbol Timing Relationship t Hold Low Time hl t Propagation Delay pd t Propagation Delay - High-to-Low pdhl t Propagation Delay - Low-to-High pdlh t ...

Page 99

Electrical and Mechanical Specifications 4.1 Timing Specifications Table 4-1. Timing Diagram Nomenclature ( Symbol Timing Relationship t Disable Time - High Disable dishz t Disable Time - Low Disable dislz t Recovery Time rec t Period per ...

Page 100

RS8228 Octal ATM Transmission Convergence PHY Device Figure 4-2. Output Waveform 4.0 Electrical and Mechanical Specifications t t fall rise t pwl t pwh t per N8228DSA Advance 4.1 Timing Specifications 2.4V 1.5V 0.4V 87 ...

Page 101

Electrical and Mechanical Specifications 4.1 Timing Specifications 4.1.1 Microprocessor Timing These figures and corresponding tables show the timing requirements and charac- teristics of the microprocessor interface. Figure 4-3. Microprocessor Timing Diagram - Asynchronous Read t s MAddr[6:0] MCs~ + ...

Page 102

RS8228 Octal ATM Transmission Convergence PHY Device Figure 4-4. MIcroprocessor Timing Diagram - Asynchronous Write t s1 MAddr[6:0] MData[7:0] MCs~ + MWr~ MRdy MRd~ (high) (low) MSyncMode Assuming 50 MHz MClk Table 4-3. Microprocessor Timing Table - Asynchronous Write Label ...

Page 103

Electrical and Mechanical Specifications 4.1 Timing Specifications Figure 4-5. Microprocessor Timing Diagram - Synchronous Read MCs~ MW/ MAs~ MAddr[6:0] t pwh Mclk MData[7:0] MRdy t enzl2 MInt~ MSyncMode (high) 90 Octal ATM Transmission Convergence PHY Device t ...

Page 104

RS8228 Octal ATM Transmission Convergence PHY Device Table 4-4. Microprocessor Timing Table - Synchronous Read Label t Pulse Width Low, MClk pwl t Pulse Width High, MClk pwh t Period, MClk (Min at 50 MHz, Max at 8 MHz) per ...

Page 105

Electrical and Mechanical Specifications 4.1 Timing Specifications Figure 4-6. Microprocessor Timing Diagram - Synchronous Write MCs~ MW/R~ t MAs~ MAddr[6:0] MData[7:0] t pwh Mclk MRdy MInt~ MSyncMode (high) 92 Octal ATM Transmission Convergence PHY Device ...

Page 106

RS8228 Octal ATM Transmission Convergence PHY Device Table 4-5. Microprocessor Timing Table - Synchronous Write Label t Pulse Width Low, MClk pwl t Pulse Width High, MClk pwh t Period, MClk (Min at 50 MHz, Max at 8 MHz) per ...

Page 107

Electrical and Mechanical Specifications 4.1 Timing Specifications Table 4-6. Framer (Line) Control Timing Table Label t Pulse Width Low, MClk pwl t Pulse Width High, MClk pwh t Period, MClk (Min MHz, Max MHz) per ...

Page 108

RS8228 Octal ATM Transmission Convergence PHY Device Figure 4-9. Framer (Line) Receive Timing Diagram LRxHld LRxData LRxMrk t pwh LRxClk Table 4-8. Framer (Line) Receive Timing Table Label t Pulse Width Low, LRxClk pwl t Pulse Width High, LRxClk pwh ...

Page 109

Electrical and Mechanical Specifications 4.1 Timing Specifications 4.1.3 UTOPIA Interface Timing These figures and corresponding tables show the timing requirements and charac- teristics of the UTOPIA interface. Figure 4-10. UTOPIA Transmit Timing Diagram UTxEnb~ UTxAddr[4:0] UTxData[15:0] UTxPrty UTxSOC UTxClk ...

Page 110

RS8228 Octal ATM Transmission Convergence PHY Device Table 4-9. UTOPIA Transmit Timing Table Label t Pulse Width Low, UTxClk pwl t Pulse Width High, UTxClk pwh t Period, UTxClk per t Setup, UTxEnb~ to the rising edge of UTxClk s1 ...

Page 111

Electrical and Mechanical Specifications 4.1 Timing Specifications Figure 4-11. UTOPIA Receive Timing Diagram URxEnb~ URxAddr[4:0] URxClk URxData[15:0] URxPrty URxSOC URxClAv 98 Octal ATM Transmission Convergence PHY Device pwl t t per pwh t t ...

Page 112

RS8228 Octal ATM Transmission Convergence PHY Device Table 4-10. UTOPIA Receive Timing Table Label t Pulse Width Low, URxClk pwl t Pulse Width High, URxClk pwh t Period, URxClk per t Setup, URxEnb~ to the rising edge of URxClk s1 ...

Page 113

Electrical and Mechanical Specifications 4.1 Timing Specifications 4.1.4 JTAG Interface Timing Figure 4-12 and Table 4-11 show the timing requirements and characteristics of the JTAG interface. Figure 4-12. JTAG Timing Diagram t rec TRST~ TMS TDI t pwh TCK ...

Page 114

RS8228 Octal ATM Transmission Convergence PHY Device 4.1.5 One-second Interface Timing Figure 4-13 and Table 4-12 show the timing requirements and characteristics of the one-second interface. Figure 4-13. One-second Timing Diagram OneSecIn t pwh1 OneSecClk OneSecOut Table 4-12. One-second Timing ...

Page 115

Electrical and Mechanical Specifications 4.2 Absolute Maximum Ratings 4.2 Absolute Maximum Ratings The absolute maximum ratings listed below are the maximum stresses that the device can tolerate without risking permanent damage. These ratings are not typi- cal of normal ...

Page 116

RS8228 Octal ATM Transmission Convergence PHY Device 4.3 DC Characteristics This section describes the DC characteristics of the RS8228. Table 4-14. DC Characteristics Parameter Power Supply (PWR) - 5V-Tolerant Input Low Voltage (VIL) - 5V-Tolerant HYS Input High Voltage (VIH) ...

Page 117

Electrical and Mechanical Specifications 4.4 Mechanical Drawing 4.4 Mechanical Drawing The RS8228 is a 272-ball BGA package. A mechanical drawing of the device is provided in Figure 4-14 and Figure 4-15. Figure 4-14. RS8228 Mechanical Drawing (Bottom View) 104 ...

Page 118

RS8228 Octal ATM Transmission Convergence PHY Device Figure 4-15. RS8228 Mechanical Drawing (Top and Side Views) 4.0 Electrical and Mechanical Specifications N8228DSA Advance 4.4 Mechanical Drawing 105 ...

Page 119

Electrical and Mechanical Specifications 4.4 Mechanical Drawing 106 Octal ATM Transmission Convergence PHY Device Advance N8228DSA RS8228 ...

Page 120

Appendix A: Related Standards The following is a list of standards relevant to the RS8228: • ATM Forum UNI Specification 94/0317 • ATM Forum - ATM User Network Interface Specification V3.1, Septem- ber 1994 • ATM Forum Utopia Level 1 ...

Page 121

Octal ATM Transmission Convergence PHY Device Advance N8228DSA RS8228 ...

Page 122

Appendix B: Boundary Scan The RS8228 supports boundary scan testing conforming to IEEE standard 1149.1a-1993 and Supplement 1149.1b, 1994. This appendix is intended to assist the customer in developing boundary scan tests for printed circuit boards and sys- tems that ...

Page 123

Figure B-1. Test Circuitry Block Diagram 227 TDI TMS TCLK TAP Controller TRST* 110 Octal ATM Transmission Convergence PHY Device 0 228-bit Boundary Scan Register 1-bit Bypass Register 2 0 3-bit Instruction Register Advance N8228DSA TDO ...

Page 124

Octal ATM Transmission Convergence PHY Device B.1 Instruction Register The Instruction Register (IR 3-bit register. When the boundary scan circuitry is reset, the IR is loaded with the BYPASS Instruction. The Capture-IR binary value is 001. The eight ...

Page 125

B.3 Boundary Scan Register The Boundary Scan Register is a 116-bit shift register that passes TDI data to the TDO in order to facilitate testing RS8228 pin connections. Table B-3 defines the Boundary Scan Register cells. Cell 0 is closest ...

Page 126

Octal ATM Transmission Convergence PHY Device Table B-3. Boundary Scan Register Cells ( Cell ...

Page 127

Table B-3. Boundary Scan Register Cells ( Cell ...

Page 128

Octal ATM Transmission Convergence PHY Device Table B-3. Boundary Scan Register Cells ( Cell 100 101 102 103 104 105 106 107 108 109 110 111 112 ...

Page 129

Table B-3. Boundary Scan Register Cells ( Cell 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 ...

Page 130

Octal ATM Transmission Convergence PHY Device Table B-3. Boundary Scan Register Cells ( Cell 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 ...

Page 131

Table B-3. Boundary Scan Register Cells ( Cell 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 ...

Page 132

Octal ATM Transmission Convergence PHY Device Table B-3. Boundary Scan Register Cells ( Cell 217 218 219 220 221 222 223 224 225 226 227 NOTE: Related Pin Cell Type Name LRxData[7] input LRxMrk[7] input LRxHld[7] input LStatOut[3][7] ...

Page 133

Octal ATM Transmission Convergence PHY Device Advance N8228DSA ...

Page 134

Appendix C: Register Summary Figure C quick reference to the RS8228’s registers. It lists all of the regis- ters and the bits that are contained in each one. N8228DSA Advance 121 ...

Page 135

Register Summary 122 Octal ATM Transmission Convergence PHY Device Advance N8228DSA RS8228 ...

Page 136

RS8228 Octal ATM Transmission Convergence PHY Device N8228DSA Advance Register Summary 123 ...

Page 137

Register Summary 124 Octal ATM Transmission Convergence PHY Device Advance N8228DSA RS8228 ...

Page 138

RS8228 Octal ATM Transmission Convergence PHY Device N8228DSA Advance Register Summary 125 ...

Page 139

Register Summary 126 Octal ATM Transmission Convergence PHY Device Advance N8228DSA RS8228 ...

Page 140

Worldwide Headquarters Rockwell Semiconductor Systems Inc. 4311 Jamboree Road, P.O. Box C Newport Beach, CA 92658-8902 Phone: (949) 221-4600 Fax: (949) 221-6375 US Northwest/Pacific Northwest Phone: (408) 249-9696 Fax: (408) 249-7113 US Southwest/Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 ...

Related keywords