MC68HC908AP64CFB Motorola, MC68HC908AP64CFB Datasheet
MC68HC908AP64CFB
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MC68HC908AP64CFB Summary of contents
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... Freescale Semiconductor, Inc. M68HC08 Microcontrollers MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MC68HC908AP64 MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 Data Sheet MC68HC908AP64/D Rev. 2.5 10/2003 ...
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Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. This product incorporates SuperFlash® technology licensed from SST. ...
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... Stop Mode — Corrected data size limits and — Updated. = 125kHz and filter components NOM MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com Page Number(s) — 167 421 data. 417, 421 DD — REG 67 125 168–193 — Corrected 207 415 101 415 MOTOROLA ...
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... Section 22. Low-Voltage Inhibit (LVI 401 Section 23. Break Module (BRK 407 Section 24. Electrical Specifications . . . . . . . . . . . . . . . . . . . . 415 Section 25. Mechanical Specifications . . . . . . . . . . . . . . . . . . 433 Section 26. Ordering Information 437 MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, (CONFIG & MOR (SCI 211 Module (IRSCI 249 Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. List of Sections Data Sheet 6 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
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... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Assignment Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Power Supply Bypassing (VDD, VDDA, VSS, VSSA Regulator Power Supply Configuration (VREG Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 35 Reserved Memory Locations ...
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... Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Section 7. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 CGM Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . 93 TBM Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . 94 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 RC Oscillator X-tal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Crystal Amplifier Input Pin (OSC1 Crystal Amplifier Output Pin (OSC2 Oscillator Enable Signal (SIMOSCEN) ...
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... SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 131 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Clock Start-up from POR or LVI Reset 132 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 133 Reset and System Initialization 133 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Go to: www.freescale.com ) . . . . . . . . . . . . . . . . . . . . . . 115 ) . . . . . . . . . . . . . . . . . . . . . 115 MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Active Resets from Internal Sources . . . . . . . . . . . . . . . . . 134 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Computer Operating Properly (COP) Reset 136 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .137 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 137 Monitor Mode Entry Module Reset 137 SIM Counter ...
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... Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 187 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .188 Pulse Width Modulation (PWM 188 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 189 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 190 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Interrupts .192 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 193 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 I/O Registers 194 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 195 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 198 TIM Channel Status and Control Registers . . . . . . . . . . . . 199 TIM Channel Registers ...
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... SCI Status Register 244 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . .246 Section 14. Infrared Serial Communications Interface Module (IRSCI) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 IRSCI Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Infrared Functional Description 253 Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... IRSCI Status Register .283 14.10.6 IRSCI Data Register 284 14.10.7 IRSCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . 285 14.10.8 IRSCI Infrared Control Register . . . . . . . . . . . . . . . . . . . . . 288 MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Infrared Transmit Encoder . . . . . . . . . . . . . . . . . . . . . . . . . 254 Infrared Receive Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 254 SCI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .255 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Transmitter ...
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... Transmission Format When CPHA = 295 Transmission Format When CPHA = 297 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . 298 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Interrupts .305 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Section 16. Multi-Master IIC Interface (MMIIC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Multi-Master IIC System Configuration . . . . . . . . . . . . . . . . . . 322 Multi-Master IIC Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 322 START Signal 323 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . .323 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Repeated START Signal ...
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... ADC Data Register 0 (ADRH0 and ADRL0 358 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3). . 360 ADC Auto-Scan Control Register (ADASCR 360 Section 18. Input/Output (I/O) Ports Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Port 366 Port A Data Register (PTA 366 Go to: www.freescale.com ) . . . . . . . . . . . . . . . . . . . . . 353 ). . . . . . . . . . . . . . . . . . . . . 353 ). . . . . . . . . . . . . 353 REFH ) . . . . . . . . . . . . . 353 REFL MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Data Direction Register (DDRA 367 Port-A LED Control Register (LEDA 369 Port 370 Port B Data Register (PTB 370 Data Direction Register B (DDRB 371 Port 373 Port C Data Register (PTC 373 Data Direction Register C (DDRC 374 Port D ...
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... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 400 Section 22. Low-Voltage Inhibit (LVI) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 Low V Detector 403 DD Low V Detector 403 REG Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .404 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . 404 LVI Status Register 404 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405 Section 23. Break Module (BRK) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Functional Description ...
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... DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 421 Section 25. Mechanical Specifications Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 48-Pin Low-Profile Quad Flat Pack (LQFP 434 44-Pin Quad Flat Pack (QFP 435 42-Pin Shrink Dual In-Line Package (SDIP 436 Section 26. Ordering Information Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... Features Features of the MC68HC908AP64 include the following: • • • • MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Section 1. General Description Table 1-1. Summary of Device Variations RAM Size Device (bytes) MC68HC908AP64 ...
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... LED drivers (sink) – 6 × 25mA open-drain I/O with pullup • Low-power design (fully static with stop and wait modes security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 24 For More Information On This Product, MC68HC908AP Family — ...
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... MCU Block Diagram Figure 1-1 MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Master reset pin (with integrated pullup) and power-on reset System protection features – Optional computer operating properly (COP) reset, driven by internal RC oscillator – Low-voltage detection with optional reset or interrupt – ...
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... PTA1/ADC1 ‡ PTA0/ADC0 PTB7/T2CH1 PTB6/T2CH0 PTB5/T1CH1 PTB4/T1CH0 † PTB3/RxD † PTB2/TxD † PTB1/SCL † PTB0/SDA † PTC7/SCRxD † PTC6/SCTxD PTC5/SPSCK PTC4/SS PTC3/MOSI PTC2/MISO # PTC1 # PTC0/IRQ2 ** PTD7/KBI7 *** PTD6/KBI6 *** PTD5/KBI5 *** PTD4/KBI4 *** PTD3/KBI3 *** PTD2/KBI2 *** PTD1/KBI1 *** PTD0/KBI0 *** . USER FLASH (bytes) 62,368 32,768 16,384 8,192 MOTOROLA ...
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... Freescale Semiconductor, Inc. 1.4 Pin Assignment PTB6/T2CH0 PTB5/T1CH1 PTB4/T1CH0 PTB3/RxD PTB2/TxD NC: No connection MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product VREG 3 4 VDD OSC1 5 OSC2 6 7 VSS 8 9 IRQ1 10 RST 11 12 Figure 1-2. 48-Pin LQFP Pin Assignments Go to: www.freescale.com ...
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... Data Sheet 28 For More Information On This Product, 1 VREG 2 3 VDD 4 OSC1 5 OSC2 6 VSS 7 8 IRQ1 9 10 RST 11 Figure 1-3. 44-Pin QFP Pin Assignments Go to: www.freescale.com PTD7/KBI7 33 32 VREFH 31 VREFL 30 PTA0/ADC0 29 PTA1/ADC1 28 PTA2/ADC2 PTA3/ADC3 27 PTA4/ADC4 26 PTA5/ADC5 25 PTA6/ADC6 24 PTA7/ADC7 23 MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... Freescale Semiconductor, Inc. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, PTD2/KBI2 1 PTD1/KBI1 2 PTD0/KBI0 3 PTB7/T2CH1 4 CGMXFC 5 PTB6/T2CH0 6 7 VREG PTB5/T1CH1 8 VDD 9 OSC1 10 11 OSC2 12 VSS 13 PTB4/T1CH0 14 IRQ1 15 PTB3/RxD 16 RST 17 PTB2/TxD 18 PTB1/SCL 19 PTB0/SDA 20 PTC7/SCRxD 21 PTC6/SCTxD Pins not available on 42-pin package ...
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... Table 1-2. VOLTAGE IN/OUT LEVEL 4 2.7 to 3.3 Out Out DDA V Out SSA (1) Out 2. TST V In REG V Out REG V Out REG V Out REG In/Out Analog V In/Out REFH V Out DD MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... I/O port with schmitt trigger inputs. : Pins as keyboard interrupts (with pullup), KBI0–KBI7. PTD7/KBI7 Notes: 1. See Section 24. Electrical Specifications MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 1-2. Pin Functions PIN DESCRIPTION for V tolerance. REG Go to: www.freescale.com ...
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... SSA C1(a) 0.1 µF + C2(a) DD Figure 1-5. Power Supply Bypassing Go to: www.freescale.com Figure 1-5 BYPASS V V DDA SSA C1(b) 0.1 µF + C2( MC68HC908AP Family — Rev. 2.5 MOTOROLA , ...
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... I/O pads, are powered by V ceramic bypass capacitor of 100 nF as bypass capacitor as close to the V MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Regulator Power Supply Configuration (VREG) is the output from the on-chip regulator. All internal logics, except REG ...
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... Freescale Semiconductor, Inc. General Description Data Sheet 34 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
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... Accessing a reserved location can have unpredictable effects on MCU operation. In the reserved locations are marked with the word Reserved or with the letter R. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Section 2. Memory Map Figure 2-1, includes: 62,368 bytes of user FLASH — MC68HC908AP64 32,768 bytes of user FLASH — ...
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... LVI Status register, LVISR • $FFCF; Mask option register, MOR (FLASH register) • $FFFF; COP control register, COPCTL Data registers are shown in locations. Data Sheet 36 For More Information On This Product, Figure 2-2. Table 2-1 MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com is a list of vector MOTOROLA ...
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... Monitor ROM 1 ↓ 447 Bytes $FFCE $FFCF Mask Option Register $FFD0 FLASH Vectors ↓ 48 Bytes $FFFF MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, MC68HC908AP32 MC68HC908AP16 $0060 RAM 1,024 Bytes RAM ↓ 2,048 Bytes Unimplemented 1,024 Bytes $085F ...
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... PTB2 PTB1 PTB0 PTC3 PTC2 PTC1 PTC0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 DDRD3 DDRD2 DDRD1 DDRD0 Reserved MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... SPI Data Register $0012 Write: (SPDR) Reset: Read: SCI Control Register 1 $0013 Write: (SCC1) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 12) MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit LEDA7 LEDA6 LEDA5 LEDA4 ...
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... RPF SCR2 SCR1 SCR0 KEYF 0 IMASK MODE ACK KBIE3 KBIE2 KBIE1 KBIE0 IRQ2F 0 IMASK2 MODE2 ACK2 SCIBD- SRC Reserved MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... Register High Write: (T1CH0H) Reset: Read: Timer 1 Channel 0 $0027 Register Low Write: (T1CH0L) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 12) MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit COPRS ...
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... Bit 0 0 PS2 PS1 PS0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Reserved MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... Reset: Read: PLL Reference Divider $003B Select Register Write: (PMDS) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 12) MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit Bit Indeterminate after reset CH1F ...
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... X = Indeterminate = Unimplemented Go to: www.freescale.com Bit 0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF Reserved MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... MMIIC CRC Data Register (MMCRDR) $004E Write: Reset: Read: MMIIC Frequency Divider $004F Register Write: (MMFDR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 12) MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit CKS SCP1 SCP0 ...
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... X = Indeterminate = Unimplemented Go to: www.freescale.com Bit TBIE TBON R TACK ADCH3 ADCH2 ADCH1 ADCH0 MODE1 MODE0 ADx ADx ADx ADx Reserved MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... Read: SIM Reset Status Register $FE01 Write: (SRSR) Reset: Read: $FE02 Reserved Write: Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 12) MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit ADx ADx ADx ADx ...
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... IF18 IF17 IF16 IF15 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 BPR0 Bit Reserved MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
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... Reset: Read: COP Control Register $FFFF Write: (COPCTL) Reset: # MOR is a non-volatile FLASH register; write by programming Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 12 of 12) MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit Bit ...
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... SCI Error Vector (High) IF11 $FFE7 SCI Error Vector (Low) $FFE8 MMIIC Interrupt Vector (High) IF10 $FFE9 MMIIC Interrupt Vector (Low) $FFEA TIM2 Overflow Vector (High) IF9 $FFEB TIM2 Overflow Vector (Low) MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com Vector MOTOROLA ...
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... Freescale Semiconductor, Inc. Priority Highest MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 2-1. Vector Addresses (Continued) INT Flag Address $FFEC TIM2 Channel 1 Vector (High) IF8 $FFED TIM2 Channel 1 Vector (Low) $FFEE TIM2 Channel 0 Vector (High) IF7 $FFEF TIM2 Channel 0 Vector (Low) ...
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... Freescale Semiconductor, Inc. Memory Map Data Sheet 52 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
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... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Go to: www.freescale.com Data Sheet 53 ...
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... Freescale Semiconductor, Inc. Random-Access Memory (RAM) Data Sheet 54 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
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... Write: (FLCR) Reset: Read: FLASH Block Protect $FE09 Register Write: (FLBPR) Reset: Figure 4-1. FLASH I/O Register Summary MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Section 4. FLASH Memory FLASH Memory Size Device (Bytes) 62,368 32,768 16,384 8,192 Bit ...
Page 56
... Programming tools are available from Motorola. Contact your local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 56 For More Information On This Product, MC68HC908AP Family — ...
Page 57
... PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, $FE08 Bit 7 6 ...
Page 58
... Data Sheet 58 For More Information On This Product, (5 µs). nvs (20 ms). erase (5 µs). nvh (1 µs), the memory can be accessed in read mode rcv MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 59
... Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, register. address range. (5 µs). ...
Page 60
... Data Sheet 60 For More Information On This Product, (Figure 4-3 shows a flowchart of the programming (5 µs). nvs (10 µs). pgs (20 µ µs). prog (5 µs). nvh (1 µs), the memory can be accessed in read mode rcv max. Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 61
... PROG This row program algorithm assumes the row programmed are initially erased. Figure 4-3. FLASH Programming Flowchart MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, 1 Set PGM bit 2 Write any data to any FLASH address within the row address range desired ...
Page 62
... For More Information On This Product, $FE09 Bit BPR7 BPR6 BPR5 BPR4 Figure 4-4. FLASH Block Protect Register (FLBPR) Go to: www.freescale.com Bit 0 BPR3 BPR2 BPR1 BPR0 16-bit memory address BPR[7:1] MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 63
... Notes: 1. Except for the mask option register ($FFCF) and the 48-byte user vectors ($FFD0–$FFFF). These FLASH locations are always protected. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 4-1 FLASH Block Protect Range BPR[7:0] $00 to $09 The entire FLASH memory is protected ...
Page 64
... Freescale Semiconductor, Inc. FLASH Memory Data Sheet 64 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 65
... The mask option register selects one of the following oscillator options: • • • MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Computer operating properly module (COP COP timeout period (2 – 2 Low-voltage inhibit (LVI LVI on V ...
Page 66
... COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD OSCSEL1 OSCSEL0 Unimplemented and Figure 5-3. Go to: www.freescale.com Bit SCIBD- SRC SSREC STOP COPD Reserved MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 67
... If LVISTOP=0, set LVIRSTD=1 before entering stop mode. LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. (See Section 22. Low-Voltage Inhibit MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Configuration & Mask Option Registers (CONFIG & MOR) $001F Bit 7 ...
Page 68
... LVI Circuit Disable Bit DD LVI circuit. (See DD (LVI).) LVI circuit disabled DD LVI circuit enabled DD LVI Circuit Disable Bit REG LVI circuit. (See REG (LVI).) LVI circuit disabled REG LVI circuit enabled REG Go to: www.freescale.com Section 22. Low- Section 22. Low- MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 69
... Reset clears this bit. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Configuration & Mask Option Registers (CONFIG & MOR) (COP).) 1 = COP module disabled ...
Page 70
... Oscillator clock, CGMXCLK, is used as clock source for SCI Data Sheet 70 For More Information On This Product, OSCCLK0 used as clock source for SCI BUS Go to: www.freescale.com Section 7. Oscillator Timebase Clock Source Internal oscillator (ICLK) RC oscillator (RCCLK) X-tal oscillator (XTAL) Not used MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 71
... The internal oscillator is a free running oscillator and is available after each POR or reset turned-off in stop mode by setting the STOP_ICLKDIS bit in CONFIG2. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Configuration & Mask Option Registers (CONFIG & MOR) $FFCF ...
Page 72
... Freescale Semiconductor, Inc. Configuration & Mask Option Registers Data Sheet 72 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 73
... Data Sheet – MC68HC908AP Family 6.1 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 6.2 Features Feature of the CPU include: • ...
Page 74
... Unaffected by reset Figure 6-2. Accumulator (A) Go to: www.freescale.com 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 0 CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Bit 0 MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 75
... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Read: Write: Reset: MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit ...
Page 76
... Read: Write: Reset: Data Sheet 76 For More Information On This Product, Bit Loaded with Vector from $FFFE and $FFFF Figure 6-5. Program Counter (PC) Go to: www.freescale.com Bit MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 77
... The half-carry flag is required for binary- coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit ...
Page 78
... Negative result 0 = Non-negative result Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 Zero result 0 = Non-zero result Data Sheet 78 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 79
... Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU. 6.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes ...
Page 80
... MCU to normal operation if the break interrupt has been deasserted. 6.7 Instruction Set Summary Table 6-1 6.8 Opcode Map The opcode map is provided in Data Sheet 80 For More Information On This Product, Section 23. Break Module provides a summary of the M68HC08 instruction set. Table 6-2. Go to: www.freescale.com (BRK).) The MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 81
... ASR opr,X ASR opr,SP BCC rel Branch if Carry Bit Clear BCLR n, opr Clear Bit MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Description ← (A) + (M) + (C) A ← (A) + (M) SP ← (SP) + (16 « M) – – – – – – IMM H:X ← ...
Page 82
... IMM DIR EXT IX2 – IX1 9EE5 ff 4 SP1 SP2 9ED5 MOTOROLA ...
Page 83
... CLRA CLRX CLRH Clear CLR opr,X CLR ,X CLR opr,SP MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Description ← (PC rel ? (Mn – – – – – PC ← (PC – – – – – – REL PC ← ...
Page 84
... SP1 9E6B DIR INH 4A 1 INH 5A 1 – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 MOTOROLA ...
Page 85
... LSL ,X LSL opr,SP LSR opr LSRA LSRX Logical Shift Right LSR opr,X LSR ,X LSR opr,SP MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Description ← ( ← ( ← ( – – M ← ( ← ( ← ( ← ...
Page 86
... FA 2 SP1 9EEA ff 4 SP2 9EDA DIR INH 49 1 INH 59 1 IX1 SP1 9E69 ff 5 DIR INH 46 1 INH 56 1 IX1 SP1 9E66 MOTOROLA ...
Page 87
... SUB opr SUB opr,X Subtract SUB opr,X SUB ,X SUB opr,SP SUB opr,SP MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Description ← (SP Pull (CCR) SP ← (SP Pull (A) SP ← (SP Pull (X) SP ← (SP Pull (PCH) SP ← ...
Page 88
... Sign extend ← Loaded with ? If : Concatenated with Set or cleared — Not affected MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com CCR 83 9 INH DIR INH 4D 1 INH 5D 1 – IX1 SP1 9E6D MOTOROLA ...
Page 89
... Freescale Semiconductor, Inc. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Central Processor Unit (CPU) Go to: www.freescale.com Central Processor Unit (CPU) Opcode Map Data Sheet 89 ...
Page 90
... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Data Sheet 90 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 91
... OSC1 pin. NOTE: The oscillator circuits are powered by the on-chip V therefore, the output swing on OSC1 and OSC2 is from V Figure MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Section 7. Oscillator (OSC) Internal oscillator RC oscillator 32.768kHz crystal (x-tal) oscillator 7-1 ...
Page 92
... CGMXCLK CGMRCLK MUX XCLK RCCLK X-TAL OSCILLATOR RC OSCILLATOR OSC1 OSC2 Figure 7-1. Oscillator Module Block Diagram Go to: www.freescale.com To TBM OSCCLK CONFIG2 OSCCLK1 MUX OSCCLK0 SIM (and COP) ICLK INTERNAL OSCILLATOR BUS CLOCK From SIM MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 93
... The internal oscillator is a free running oscillator and is available after each POR or reset turned-off in stop mode by setting the STOP_ICLKDIS bit in CONFIG2. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, 5.5 Mask Option Register $FFCF Bit OSCSEL1 OSCSEL0 ...
Page 94
... XCLKEN Figure 7-3. Configuration Register 2 (CONFIG2) OSCCLK0 to: www.freescale.com 5 Bit SCIBDSRC Timebase Clock Source Internal oscillator (ICLK) RC oscillator (RCCLK) X-tal oscillator (XCLK) Not used , is a free ICLK MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 95
... R and one C. Component values should have a tolerance less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components: • • MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, shows the logical representation of components of the From SIM SIMOSCEN CONFIG2 ...
Page 96
... To Clock Selection MUX SIMOSCEN RCCLK EN RC OSCILLATOR OSC1 for component value requirements. V REG R EXT Figure 7-5. RC Oscillator Figure (32.768kHz (can also be a fixed capacitor (optional to: www.freescale.com From SIM BUS CLOCK OSC2 C EXT 7-6. This figure shows only MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 97
... I/O Signals The following paragraphs describe the oscillator I/O signals. 7.6.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, From SIM SIMOSCEN CONFIG2 MCU Section 24 ...
Page 98
... The OSCCLK is the reference clock that drives the timebase module. See Section 12. Timebase Module 7.7 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. Data Sheet 98 For More Information On This Product, (TBM). MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 99
... STOP_ICLKDIS bit to logic 1 before entering stop mode. 7.8 Oscillator During Break Mode The oscillator continues to drive CGMXCLK when the device enters the break state. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Go to: www.freescale.com Oscillator (OSC) Oscillator During Break Mode Data Sheet ...
Page 100
... Freescale Semiconductor, Inc. Oscillator (OSC) Data Sheet 100 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 101
... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference Low-frequency crystal operation with low-power operation and high-output frequency resolution Programmable prescaler for power-of-two increases in frequency ...
Page 102
... CGMPCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 8-1 Figure 8-2 Data Sheet 102 For More Information On This Product, shows the structure of the CGM summary of the CGM registers. Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 103
... PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE DIVIDER R RDS[3:0] V DDA PHASE DETECTOR LOCK DETECTOR LOCK MUL[11:0] N CGMVDV FREQUENCY DIVIDER MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, (OSC). ICLK OSCCLK CGMXCLK MUX CGMRCLK CGMRCLK BCS CGMXFC V SSA VPR[1:0] VRS[7: VOLTAGE ...
Page 104
... Bit 0 PRE1 PRE0 VPR1 VPR0 MUL11 MUL10 MUL9 MUL8 MUL3 MUL2 MUL1 MUL0 VRS3 VRS2 VRS1 VRS0 RDS3 RDS2 RDS1 RDS0 Reserved MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 105
... The PLL consists of these circuits: • • • • • • • MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Section 7. Oscillator (OSC) Section 12. Timebase Module (TBM) Voltage-controlled oscillator (VCO) Reference divider Frequency pre-scaler Modulo VCO frequency divider Phase detector ...
Page 106
... With an external crystal RDV RCLK for more information.) 8.3.4 Acquisition and Tracking . The circuit determines the mode of the PLL and the lock RDV Go to: www.freescale.com . VRS by a RCLK , is VCLK /(N × (See VDV VCLK Modes. The value of the MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 107
... Interrupts MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency ...
Page 108
... Such systems typically operate well below f BUSMAX Data Sheet 108 For More Information On This Product, 8.5.2 PLL Bandwidth Control Modes.) 8.8 Acquisition/Lock Time for more information.) 8.8 Acquisition/Lock Time for more information.) Register to: www.freescale.com Register 8.3.4 8.5.1 PLL MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 109
... Choose the desired bus frequency Choose a practical PLL reference frequency, f MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear ...
Page 110
... RCLK R f VCLK ---------- - f = BUS P × to: www.freescale.com , and the VCLK ) Specifications. to RCLK cannot meet this RCLK that gives the RCLK ⎛ ⎞ ⎫ f VCLKDES ⎜ ⎟ ⎬ integer ------------------------- - ⎝ ⎠ f ⎭ RCLK ⎞ ⎟ P ⎠ MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 111
... Calculate and verify the adequacy of the VCO programmed 8. Verify the choice and L by comparing f NOTE: Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, this table: Frequency Range 0 < f < 9,830,400 VCLK 9,830,400 ≤ ...
Page 112
... 32.768 kHz MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 113
... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product value for interpreted exactly the same as a value value for L disables the PLL and prevents its selection as the source for the base clock ...
Page 114
... For More Information On This Product, shows the external components for the PLL: BYP 8.8 Acquisition/Lock Time Specifications MCU CGMXFC 1 kΩ 0.22 µF Figure 8-3. CGM External Connections Go to: www.freescale.com for V V SSA DDA BYP 0.1 µF MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 115
... RC oscillator circuit, or the internal oscillator circuit. 8.4.5 CGM Reference Clock (CGMRCLK) CGMRCLK is a buffered version of CGMXCLK, this clock is the reference clock for the phase-locked-loop circuit. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, 8-3.) ) DDA is a power pin used by the analog portions of the PLL. Connect the ...
Page 116
... PLL reference divider select register (PMDS) (See Data Sheet 116 For More Information On This Product, 8.5.1 PLL Control Register.) 8.5.2 PLL Bandwidth Control 8.5.3 PLL Multiplier Select Registers.) 8.5.4 PLL VCO Range Select 8.5.5 PLL Reference Divider Select Go to: www.freescale.com Register.) Register.) Register.) MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 117
... Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, $0036 Bit ...
Page 118
... Data Sheet 118 For More Information On This Product, 8.3.8 Base Clock Selector Circuit.) Reset clears the BCS bit. 8.3.8 Base Clock Selector Circuit.) 8.3.3 PLL Circuits PLL.) PRE1 and PRE0 cannot be written when MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com 8.3.8 and 8.3.6 MOTOROLA ...
Page 119
... NOTE: Do not program value of 3. 8.5.2 PLL Bandwidth Control Register The PLL bandwidth control register (PBWC): • • • • MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 8-2. PRE1 and PRE0 Programming PRE1 and PRE0 PLL, and 8 ...
Page 120
... Reset clears this bit, enabling acquisition mode Tracking mode 0 = Acquisition mode Data Sheet 120 For More Information On This Product, $0037 Bit LOCK 0 AUTO ACQ Unimplemented Go to: www.freescale.com Bit Reserved MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 121
... Reset initializes the registers to $0040 for a default multiply value of 64. NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, $0038 Bit ...
Page 122
... Figure 8-8. PLL VCO Range Select Register (PMRS) PLL, and Exceptions.) A value of $00 in the VCO 8.3.8 Base Clock Selector Circuit 8.3.7 Special Programming Exceptions.). Reset initializes the Go to: www.freescale.com Bit 0 VRS3 VRS2 VRS1 VRS0 8.3.3 PLL Circuits, 8.5.1 PLL Control Register.), . VRS[7:0] VRS 8.3.7 MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 123
... The reference divider select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). NOTE: The default divide value recommended for all applications. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, $003B Bit ...
Page 124
... PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. Data Sheet 124 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 125
... With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, CONFIG2) if continuos clock is required in stop mode. Go to: www.freescale.com ...
Page 126
... Acquisition and lock times are designed short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. Data Sheet 126 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 127
... PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, . This frequency is the input to the phase RDV and the R value programmed in the reference divider ...
Page 128
... For More Information On This Product, 8.8.2 Parametric Influences on Reaction Figure 8-10 is recommended when using Figure 8-10 CGMXFC 1 kΩ 0.22 µF V SSA (a) Figure 8-10. PLL Filter MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com Time, the Figure 8-10 (a) is used for (b) is used in low-cost CGMXFC 0.22 µF V SSA (b) MOTOROLA ...
Page 129
... CPU and exception timing. The SIM is responsible for: • • • • • Table 9-1 MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Figure 9-1. Table 9-1 Bus clock generation and control for CPU and peripherals: – Stop/wait/reset/break entry and recovery – Internal clock control ...
Page 130
... CPU WAIT (FROM CPU) SIMOSCEN (TO CGM, OSC) COP CLOCK ICLK (FROM OSC) CGMOUT (FROM CGM) INTERNAL CLOCKS LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 131
... The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in from either an external oscillator or from the on-chip PLL. (See 8. Clock Generator Module MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit ...
Page 132
... TO TBM CGMXCLK TO TIM, ADC ICLK SIM COUNTER SYSTEM INTEGRATION MODULE CGMOUT ÷ 2 SIMDIV2 CGMVCLK TO PWM Figure 9-3. CGM Clock Signals Go to: www.freescale.com SIMOSCEN IT12 TO REST OF MCU BUS CLOCK IT23 GENERATORS TO REST OF MCU PTB0 MONITOR MODE USER MODE MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 133
... An internal reset clears the SIM counter (see external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). (See MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Power-on reset module (POR) External reset pin (RST) ...
Page 134
... For More Information On This Product, Table 9-2 shows the relative timing. Table 9-2. PIN Bit Set Timing Number of Cycles Required to Set PIN POR/LVI All others PC Figure 9-4. External Reset Timing Figure 9-6). 9-5. Go to: www.freescale.com for details. 4163 (4096 + ( VECT H VECT L Figure 9-5). An MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 135
... At power-on, these events occur: • • • • • • MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, RST PULLED LOW BY MCU 32 CYCLES Figure 9-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR Figure 9-6 ...
Page 136
... V on the RST pin disables the COP module. TST Data Sheet 136 For More Information On This Product CYCLES CYCLES Figure 9-7. POR Recovery 4 ICLK cycles, drives the COP counter. The COP should be Go to: www.freescale.com $FFFE $FFFF MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 137
... The SIM actively pulls down the RST pin for all internal reset sources. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, voltage falls to the LVI voltage. The LVI bit in the SIM reset TRIPF Section 10 ...
Page 138
... The SIM counter is free-running after all reset states. 9.3.2 Active Resets from Internal Sources internal reset recovery sequences.) Data Sheet 138 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com (See 9.6.2 Stop Mode (See for counter control and MOTOROLA ...
Page 139
... MODULE INTERRUPT I-BIT IAB SP – 4 IDB R/W Figure 9-9. Interrupt Recovery Timing MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Interrupts: – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) Reset Break interrupts Figure 9-8 shows interrupt recovery timing. SP – – ...
Page 140
... IRQ1 YES INTERRUPT MANY INTERRUPTS LOAD PC WITH INTERRUPT VECTOR AS EXIST ON CHIP FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? NO Figure 9-10. Interrupt Processing Go to: www.freescale.com STACK CPU REGISTERS SET I-BIT UNSTACK CPU REGISTERS EXECUTE INSTRUCTION MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 141
... If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, CLI LDA ...
Page 142
... Bit IF6 IF5 IF4 IF3 Reserved Figure 9-12. Interrupt Status Register 1 (INT1) Table 9-3. Go to: www.freescale.com Bit 0 IF2 IF1 MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 143
... Freescale Semiconductor, Inc. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 9-3. Interrupt Sources INT Vector Priority Flag Address Lowest $FFD0 — $FFD1 $FFD2 IF21 $FFD3 $FFD4 IF20 $FFD5 $FFD6 IF19 $FFD7 $FFD8 IF18 $FFD9 $FFDA IF17 $FFDB $FFDC ...
Page 144
... IF21 IF20 IF19 Reserved Figure 9-14. Interrupt Status Register 3 (INT3) Table 9-3. Go to: www.freescale.com Bit 0 IF10 IF9 IF8 IF7 Bit 0 IF18 IF17 IF16 IF15 MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 145
... Upon leaving break mode, execution of the second step will clear the flag as normal. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, (BRK).) The SIM puts the CPU into the Go to: www.freescale.com ...
Page 146
... WAIT ADDR WAIT ADDR + 1 PREVIOUS DATA NEXT OPCODE last instruction. Figure 9-15. Wait Mode Entry Timing and Figure 9-17 show the timing for WAIT recovery. Go to: www.freescale.com SAME SAME SAME SAME MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 147
... ICLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, IAB $6E0B $6E0C IDB $A6 ...
Page 148
... IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA NEXT OPCODE R/W instruction. Figure 9-18. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + to: www.freescale.com SAME SAME SAME SAME SP – – – 3 MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 149
... SBSW,SBSR, RETURN TST LOBYTE,SP BNE DOLO DEC HIBYTE,SP DOLO DEC LOBYTE,SP RETURN PULH RTI MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, $FE00 Bit Reserved Figure 9-20. SIM Break Status Register (SBSR Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt ...
Page 150
... For More Information On This Product, $FE01 Bit POR PIN COP ILOP Unimplemented Figure 9-21. SIM Reset Status Register (SRSR) $FFFE and $FFFF are $FF after POR while IRQ1 = V Go to: www.freescale.com Bit 0 ILAD MODRST LVI MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 151
... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product Last reset caused by the LVI circuit 0 = POR or read of SRSR ...
Page 152
... Freescale Semiconductor, Inc. System Integration Module (SIM) Data Sheet 152 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 153
... No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Section 10. Monitor ROM (MON) Normal user-mode pin functionality ...
Page 154
... V Data Sheet 154 For More Information On This Product, Figure 10-1 shows an example circuit used to enter monitor on IRQ1. TST Go to: www.freescale.com , if reset vector is TST , is applied to TST MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 155
... Affects high voltage entry to monitor mode only (SW2 at position C): SW1: Position A — Bus clock = OSC1 ÷ 4 SW1: Position B — Bus clock = OSC1 ÷ See Table 24-4 for V voltage level requirements. TST MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, V REG 4.9152MHz/9.8304MHz (50% DUTY) OSC1 32.768kHz 6– µ ...
Page 156
... PLL to boost the external SS 32.768 kHz to an internal bus frequency of 2.4576 MHz is applied to IRQ1 and PTB0 is low upon monitor mode entry applied to IRQ1 upon monitor mode TST Go to: www.freescale.com is applied to IRQ1. TST then all port A pin DD SS MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 157
... Freescale Semiconductor, Inc. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Monitor ROM (MON) Go to: www.freescale.com Monitor ROM (MON) Functional Description Data Sheet 157 ...
Page 158
... IRQ1 pin. DD 10.4 Security.) After the security bytes, the MCU sends a MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com , to TST on IRQ1 (condition set 1), is applied to either IRQ1 TST is maintained on the TST is applied to RST after TST was applied to TST is TST Figure 10-1 by MOTOROLA ...
Page 159
... Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST low will not exit monitor mode in this situation. Table 10-2 mode vectors. Modes Monitor MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, POR RESET IS VECTOR BLANK? YES MONITOR MODE EXECUTE ...
Page 160
... Figure 10-4. Break Transaction DD Go to: www.freescale.com NEXT START STOP BIT 5 BIT 6 BIT 7 BIT BIT 2-STOP BIT DELAY BEFORE ZERO ECHO upon entry into TST on IRQ1, then the divide by ratio MC68HC908AP Family — Rev. 2.5 MOTOROLA SS ...
Page 161
... NOTE: Wait one bit time after each echo before sending the next byte. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, lists external frequencies required to achieve a standard Table 10-3. Monitor Baud Rate Selection ...
Page 162
... Read byte from memory 2-byte address in high-byte:low-byte order Returns contents of specified address $4A Command Sequence ADDRESS ADDRESS ADDRESS READ HIGH HIGH LOW Go to: www.freescale.com ADDRESS DATA LOW RETURN ADDRESS DATA DATA LOW ADDRESS DATA LOW RETURN MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 163
... FROM HOST WRITE ECHO Description Operand Data Returned Opcode MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 10-5. WRITE (Write Memory) Command Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence ADDRESS ADDRESS ...
Page 164
... DATA IWRITE IWRITE ECHO Table 10-8. READSP (Read Stack Pointer) Command Reads stack pointer None Returns incremented stack pointer value ( high-byte:low-byte order $0C Command Sequence FROM HOST READSP READSP ECHO Go to: www.freescale.com DATA SP SP HIGH LOW RETURN MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 165
... The READSP command returns the incremented stack pointer value The high and low bytes of the program counter are at addresses and MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 10-9. RUN (Run User Program) Command Executes PULH and RTI instructions ...
Page 166
... Wait 1 bit time before sending next byte. Data Sheet 166 For More Information On This Product, Figure 4096 + 32 ICLK CYCLES 256 BUS CYCLES (MINIMUM) FROM HOST FROM MCU Figure 10-8. Monitor Mode Entry Timing MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com 10-8 MOTOROLA ...
Page 167
... RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Go to: www.freescale.com Monitor ROM (MON) ...
Page 168
... Emulated EEPROM write. Data size ranges from bytes at a time. Emulated EEPROM read. Data size ranges from bytes at a time. Figure 10-9. MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com Call Stack Used Address (bytes) $FC34 15 $FCE4 9 $FC00 7 $FF24 17 $FF28 11 $FF36 30 $FD5B 18 MOTOROLA ...
Page 169
... Figure 10-9. Data Block Format for ROM-Resident Routines The control and data bytes are described below. • • • • MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, FILE_PTR $XXXX BUS SPEED (BUS_SPD) ADDRESS AS POINTER DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) ...
Page 170
... Data Sheet 170 For More Information On This Product, Table 10-11. PRGRNGE Routine PRGRNGE Program a range of locations $FC34 15 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Start address high (ADDRH) Start address (ADDRL) Data 1 (DATA1) : Data N (DATAN) MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 171
... Freescale Semiconductor, Inc. FILE_PTR: BUS_SPD DATASIZE START_ADDR DATAARRAY PRGRNGE FLASH_START INITIALISATION: MAIN: MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, ORG RAM : DS Indicates 4x bus frequency DS Data size to be programmed DS FLASH start address DS Reserved data array EQU $FC34 EQU $EE00 ...
Page 172
... For More Information On This Product, Table 10-12. ERARNGE Routine ERARNGE Erase a page or the entire array $FCE4 9 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) 10.5.1 PRGRNGE). EQU $FCE4 BSR INITIALISATION : : LDHX #FILE_PTR JSR ERARNGE : Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 173
... The coding example below is to retrieve 64 bytes of data starting from $EE00 in FLASH. The Initialization subroutine is the same as the coding example for PRGRNGE (see LDRNGE MAIN: MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 10-13. LDRNGE Routine LDRNGE Loads data from a range of locations $FC00 ...
Page 174
... Data Sheet 174 For More Information On This Product, Table 10-14. MON_PRGRNGE Routine MON_PRGRNGE Program a range of locations, in monitor mode $FF24 17 bytes Bus speed Data size Starting address (high byte) Starting address (low byte) Data 1 : Data N MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com 10.5.1 MOTOROLA ...
Page 175
... ERARNGE), except that MON_ERARNGE returns to the main program via an SWI instruction. After a MON_ERARNGE call, the SWI instruction will return the control back to the monitor code. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 10-15. MON_ERARNGE Routine MON_ERARNGE Erase a page or the entire array, in monitor mode ...
Page 176
... For More Information On This Product, Table 10-16. EE_WRITE Routine EE_WRITE Emulated EEPROM write. Data size ranges from bytes at a time. $FF36 30 bytes Bus speed (BUS_SPD) (1) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) Data 1 : Data N MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com (2) (1) MOTOROLA ...
Page 177
... The data array size is 15 bytes, and the bus speed is 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Figure 10-10). The page control operations ...
Page 178
... Indicates 4x bus frequency DS Data size to be programmed DS FLASH starting address DS Reserved data array EQU $FF36 EQU $EE00 ORG FLASH MOV #20, BUS_SPD MOV #15, DATASIZE LDHX #FLASH_START STHX START_ADDR RTS BSR INITIALISATION : : LHDX #FILE_PTR JSR EE_WRITE Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 179
... RAM. The initialization subroutine is the same as the coding example for EE_WRITE (see EE_READ MAIN: MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Table 10-17. EE_READ Routine EE_READ Emulated EEPROM read. Data size ranges from bytes at a time. ...
Page 180
... FLASH page boundary and the data size 15. If the FLASH page is programmed with a data array with a different size, the EE_READ call will be ignored. Data Sheet 180 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 181
... MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Two input capture/output compare channels: – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action Buffered and unbuffered pulse-width-modulation (PWM) signal generation ...
Page 182
... For More Information On This Product, 11-1. The generic pin names appear in the text that follows. Table 11-1. Pin Name Conventions TIM1 PTB4/T1CH0 TIM2 PTB6/T2CH0 shows the structure of the TIM. The central component of Go to: www.freescale.com T[1,2]CH0 T[1,2]CH1 PTB5/T1CH1 PTB7/T2CH1 MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 183
... Figure 11-2 NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC and T2SC. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, PRESCALER SELECT PS2 PS1 PS0 ...
Page 184
... Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 185
... Control Register Write: (T2SC0) Reset: Read: Timer 2 Channel 0 $0031 Register High Write: (T2CH0H) Reset: Figure 11-2. TIM I/O Register Summary (Sheet MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit Bit Indeterminate after reset Bit 7 6 ...
Page 186
... CH1F 0 CH1IE MS1A Bit Indeterminate after reset Bit Indeterminate after reset = Unimplemented Go to: www.freescale.com Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 187
... Use the following methods to synchronize unbuffered changes in the output compare value on channel x: • • MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, 11.4.3 Output When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine ...
Page 188
... TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. Data Sheet 188 For More Information On This Product, shows, the output compare value in the TIM channel MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 189
... PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, 11.9.1 TIM Status and Control OVERFLOW ...
Page 190
... TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. Data Sheet 190 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com MOTOROLA ...
Page 191
... PWM pulse width to a new, much larger value the TIM status control register (TSC), clear the TIM stop bit, MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, a. Stop the TIM counter by setting the TIM stop bit, TSTOP. ...
Page 192
... CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register. 11.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. Data Sheet 192 For More Information On This Product, Registers.) MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com 11.9.4 TIM Channel MOTOROLA ...
Page 193
... BCFE is at logic 0. After the break, doing the second step clears the status bit. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, 9.7.3 SIM Break Flag Control Go to: www.freescale.com ...
Page 194
... TIM counter registers (TCNTH:TCNTL) • TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0, TSC1) • TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L) Data Sheet 194 For More Information On This Product, MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com 11.3 Pin Name MOTOROLA ...
Page 195
... TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Enables TIM overflow interrupts Flags TIM overflows ...
Page 196
... Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ MC68HC908AP Family — Rev. 2.5 Go to: www.freescale.com TIM Clock Source Not available MOTOROLA ...
Page 197
... Address: T1CNTH, $0021 and T2CNTH, $002C Read: Write: Reset: Address: T1CNTL, $0022 and T2CNTL, $002D Read: Write: Reset: MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Bit Bit ...
Page 198
... For More Information On This Product, Bit Bit Bit Bit to: www.freescale.com Bit Bit Bit Bit MC68HC908AP Family — Rev. 2.5 MOTOROLA ...
Page 199
... Read: Write: Reset: Figure 11-10. TIM Channel 1 Status and Control Register (TSC1) MC68HC908AP Family — Rev. 2.5 MOTOROLA For More Information On This Product, Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation ...
Page 200
... MSxA — Mode Select Bit A When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See 1 = Unbuffered output compare/PWM operation 0 = Input capture operation Data Sheet 200 For More Information On This Product, Table 11-3. Go to: www.freescale.com MC68HC908AP Family — Rev. 2.5 MOTOROLA ...