SC2200UCL-266 National Semiconductor, SC2200UCL-266 Datasheet
SC2200UCL-266
Available stocks
Related parts for SC2200UCL-266
SC2200UCL-266 Summary of contents
Page 1
... Bus I/F GPIO Audio Codec I/F LPC I/F National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode and VSA are trademarks of National Semiconductor Corporation. For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks. © 2002 National Semiconductor Corporation • The Core Logic module includes: PC/AT functionality, a ® ...
Page 2
Features General Features 32-Bit x86 processor 300 MHz, with MMX instruction set support Memory controller with 64-bit SDRAM interface 2D graphics accelerator CRT controller with hardware video accelerator CCIR-656 video input port with direct video for full screen ...
Page 3
Core Logic Module Audio Codec Interface: — AC97/AMC97 (Rev. 2.0) codec interface — Legacy audio emulation using XpressAUDIO — Six DMA channels PC/AT Functionality: — Programmable Interrupt Controller (PIC), 8259A-equivalent — Programmable Interval Timer (PIT), 8254-equivalent — DMA Controller (DMAC), ...
Page 4
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Table of Contents (Continued) 3.0 General Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Table of Contents (Continued) 4.5.3 RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
Table of Contents (Continued) 5.2.6 AT Compatibility Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
Table of Contents (Continued) 6.0 Video Processor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
Table of Contents (Continued) 8.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
Architecture Overview As illustrated in Figure 1-1, the SC2200 contains the follow- ing modules in one integrated device: • GX1 Module: — Combines advanced CPU performance with MMX support, fully accelerated 2D graphics, a 64-bit synchronous DRAM (SDRAM) interface ...
Page 11
Architecture Overview (Continued) 1.1 GX1 MODULE The GX1 processor (silicon revision 8.1.1) is the central module of the SC2200. For detailed information regarding the GX1 module, refer to the G eode GX1 Processor Series datasheet and the Geode GX1 Processor ...
Page 12
Architecture Overview (Continued) Table 1-2. SC2200 Memory Controller Registers Bit Description GX_BASE+ 8400h-8403h 31:30 MDCTL (MD[63:0] Drive Strength strongest weakest. 29 RSVD (Reserved) Write as 0. 28:27 MABACTL (MA[12:0] and BA[1:0] Drive Strength strongest, ...
Page 13
Architecture Overview (Continued) Table 1-2. SC2200 Memory Controller Registers (Continued) Bit Description GX_BASE+8404h-8407h 31:14 RSVD (Reserved). Write as 0. 13:12 SDCLKCTL (SDCLK High Drive/Slew Control). Controls the high drive and slew rate of SDCLK[3:0] and SDCLK_OUT strongest, 00 ...
Page 14
Architecture Overview (Continued) Table 1-2. SC2200 Memory Controller Registers (Continued) Bit Description 6:4 SODIMM_PG_SZ (SODIMM Page Size - Banks 0 and 1). Selects the page size of SODIMM: 000 010 001 011 ...
Page 15
Architecture Overview (Continued) Table 1-2. SC2200 Memory Controller Registers (Continued) Bit Description GX_BASE+8414h-8417h 31:18 RSVD (Reserved). Write (Test Enable TEST[3:0]). 0: TEST[3:0] are driven low (normal operation). 1: TEST[3:0] pins are used to output test information ...
Page 16
Architecture Overview (Continued) 1.1.2 Fast-PCI Bus The GX1 module communicates with the Core Logic mod- ule via a Fast-PCI bus that can work MHz. The Fast-PCI bus is internal for the SC2200 and is connected to ...
Page 17
Architecture Overview (Continued) • LPC: See Section 2.4.8 "Low Pin Count (LPC) Bus Inter- face Signals" on page 67. • Sub-ISA: See Section 2.4.7 "Sub-ISA Interface Signals" on page 66, Section 5.2.5 "Sub-ISA Bus Interface" on page 156, and Section ...
Page 18
Signal Definitions This section defines the signals and describes the external interface of the SC2200. Figure 2-1 shows the signals organized by their functional groups. Where signals are multiplexed, the default signal name is listed first and is separated ...
Page 19
Signal Definitions (Continued) POWER_EN OVER_CUR# DPOS_PORT1 USB DNEG_PORT1 Interface DPOS_PORT2 DNEG_PORT2 DPOS_PORT3 DNEG_PORT3 SIN1 SIN2+SDTEST3 SOUT1+CLKSEL1 SOUT2+CLKSEL2 Serial Ports GPIO7+RTS2#+IDE_DACK1#+SDTEST0 (UARTs)/IDE GPIO8+CTS2#+IDE_DREQ1+SDTEST4 GPIO18+DTR1#/BOUT1 Interface GPIO6+DTR2#/BOUT2+IDE_IOR1#+SDTEST5 GPIO11+RI2#+IRQ15 GPIO9+DCD2#+IDE_IOW1#+SDTEST2 GPIO10+DSR2#+IDE_IORDY1+SDTEST1 IR Port IRRX1+SIN3 Interface IRTX+SOUT3 BIT_CLK SDATA_OUT+TFT_PRSNT SDATA_IN AC97 Audio SDATA_IN2 Interface ...
Page 20
Signal Definitions (Continued) 2.1 BALL ASSIGNMENTS The SC2200 is highly configurable as illustrated in Figure 2-1 on page 18. Strap options and register programming are used to set various modes of operation and specific signals on specific balls. This section ...
Page 21
Signal Definitions (Continued AD29 AD26 AD22 ...
Page 22
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number 1 Ball I/O Buffer No. Signal Name (PU/PD) Type A1 V GND --- PWR --- IO A3 AD29 I PCI O PCI ...
Page 23
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type B10 AD15 I PCI O PCI A15 O O PCI B11 V PWR --- IO ...
Page 24
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type IDE_DATA9 I C20 TS1 TS 1/4 DDC_SDA I C21 ...
Page 25
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type F1 IOR 3/5 DOCR 3/5 GPIO14 I ( ...
Page 26
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type M4 V GND --- SS M28 V GND --- SS MD7 I M29 T ...
Page 27
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type PD6 I 14/14 TFTD1 O O 1/4 F_AD6 O O ...
Page 28
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type STB#/WRITE AB1 14/14 TFTD17 O 1/4 O F_FRAME 14/14 AFD#/DSTRB# O ...
Page 29
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type AH8 VPD4 AH9 VPD0 AH10 V GND --- SS AH11 V ...
Page 30
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type MD22 I AJ27 T TS 2/5 4 MD19 I AJ28 T TS ...
Page 31
Signal Definitions (Continued) Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type MD57 I AL17 T TS 2/5 4 MD60 I AL18 T TS ...
Page 32
Signal Definitions (Continued) Table 2-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name Signal Name Ball No. A0 A17 A1 D16 A2 A18 A3 A15 A4 A16 A5 A14 A6 C15 A7 B14 A8 C14 A9 B13 A10 C13 ...
Page 33
Signal Definitions (Continued) Table 2-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. F_C/BE2# T3 F_C/BE3# T4 F_DEVSEL# AL15 F_FRAME# AB1 F_GNT0# AK14 F_IRDY# W1 F_STOP# AJ15 F_TRDY# AL14 FP_VDD_ON B23, AL16 FPCI_MON D3 ...
Page 34
Signal Definitions (Continued) Table 2-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. MD26 AK22 MD27 AL22 MD28 AH23 MD29 AJ23 MD30 AK23 MD31 AL23 MD32 U31 MD33 U29 MD34 V31 MD35 V30 MD36 ...
Page 35
Signal Definitions (Continued) Table 2-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. V (Total of 25) D11, D13, D15, CORE D17, D19, D21, L4, L28, N4, N28, R4, R28, T30, U4, U28, W4, ...
Page 36
Signal Definitions (Continued AD30 PCK0 ...
Page 37
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number 1 Ball I/O Buffer No. Signal Name (PU/PD) Type A1 V GND --- PWR --- IO A3 AD30 I PCI O PCI ...
Page 38
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type B6 AD23 I PCI O PCI A23 O O PCI B7 V GND --- SS ...
Page 39
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type C16 AV GND --- SSPLL2 SLCT I IN 6,2 C17 T TFTD15 O O 1/4 F_C/BE3# O ...
Page 40
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type D13 V GND --- SS D14 V PWR --- IO D15 AV PWR --- CCCRT D16 VREF ...
Page 41
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type G28 V GND --- SS G29 V PWR --- IO G30 V GND --- SS G31 VPD7 ...
Page 42
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type M2 AD7 I PCI O PCI PCI M3 V PWR --- IO ...
Page 43
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type T18 V GND --- SS T19 V GND --- SS T28 V PWR --- CORE T29 V ...
Page 44
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type AA1 IDE_RST 1/4 TFTDCK O O 1/4 AA2 IDE_DATA7 I TS1 TS 1/4 ...
Page 45
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type AG29 DQM6 O O 2/5 AG30 DQM2 O O 2/5 MD55 I AG31 T ...
Page 46
Signal Definitions (Continued) Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) 1 Ball I/O Buffer No. Signal Name (PU/PD) Type AK5 GPWIO1 I ( 100 2/ PWRCNT1 O OD AK6 ...
Page 47
Signal Definitions (Continued) Table 2-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name Signal Name Ball No A10 L3 ...
Page 48
Signal Definitions (Continued) Table 2-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. F_C/BE3# C17 F_DEVSEL# V31 F_FRAME# A22 F_GNT0# U31 F_IRDY# B20 F_STOP# U29 F_TRDY# U30 FP_VDD_ON V30, AB1 FPCI_MON A4 FPCICLK B18 ...
Page 49
Signal Definitions (Continued) Table 2-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. MD27 AC30 MD28 AE31 MD29 AD29 MD30 AD30 MD31 AD31 MD32 AJ15 MD33 AJ16 MD34 AH16 MD35 AK17 MD36 AJ17 MD37 ...
Page 50
Signal Definitions (Continued) Table 2-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. V (Total of 43) A2, A30, B2, B13, IO B16, B19, B31, C3, C7, C10, C22, C25, C29, D14, D18, D23, ...
Page 51
Signal Definitions (Continued) 2.2 STRAP OPTIONS Several balls are read at power-up that set up the state of the SC2200. These balls are typically multiplexed with other functions that are outputs after the power-up sequence is complete. The SC2200 must ...
Page 52
Signal Definitions (Continued) 2.3 MULTIPLEXING CONFIGURATION The tables that follow list multiplexing options and their configurations. Certain multiplexing options may be chosen per signal; others are available only for a group of signals. Where ever a GPIO pin is multiplexed ...
Page 53
Signal Definitions (Continued) Table 2-7. Two-Signal/Group Multiplexing (Continued) EBGA TEPBGA Signal Ball No. AJ12 N29 GPIO12 AL11 M29 GPIO13 Ball No. A28 AG1 GPIO18 Ball No. J3 C11 IRTX J28 AK8 IRRX1 Ball No. AJ11 M28 GPIO32 AL10 L31 GPIO33 ...
Page 54
Signal Definitions (Continued) Table 2-8. Three-Signal/Group Multiplexing Default EBGA TEPBGA Signal Ball No. Sub-ISA F1 D9 IOR IOW# Ball No. GPIO AL15 V31 GPIO16 Ball No. GPIO H4 C9 GPIO19 Ball No. Parallel Port U3 B18 ACK# AB2 ...
Page 55
Signal Definitions (Continued) Table 2-8. Three-Signal/Group Multiplexing (Continued) Default EBGA TEPBGA Signal Ball No. Internal Test AL16 V30 GXCLK 1. The combination of PMR[21 and PMR[ undefined and should not be used. 2. The combination ...
Page 56
Signal Definitions (Continued) 2.4 SIGNAL DESCRIPTIONS Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identi- cal information. 2.4.1 System Interface Ball No. Signal Name EBGA TEPBGA CLKSEL1 B27 AF3 CLKSEL0 F3 ...
Page 57
Signal Definitions (Continued) 2.4.1 System Interface (Continued) Ball No. Signal Name EBGA TEPBGA DID1 D2 DID0 D4 POR# J29 AH9 X32I C30 AJ2 X32O D29 AJ3 X27I A29 AG3 X27O D27 AH2 CLK27M A23 AA4 PCIRST# D1 2.4.2 Memory Interface ...
Page 58
Signal Definitions (Continued) 2.4.2 Memory Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA CS1# AK29 AH27 CS0# P29 AL12 RASA# N31 AK12 CASA# N30 AJ12 WEA# N29 AH12 DQM7 AJ20 AB31 DQM6 AJ26 AG29 DQM5 AC30 AK21 DQM4 T28 ...
Page 59
Signal Definitions (Continued) 2.4.2 Memory Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA SDCLK_OUT AH28 AK28 2.4.3 Video Port Interface Signals Ball No. Signal Name EBGA TEPBGA VPD7 AJ6 G31 VPD6 AJ7 H28 VPD5 AL6 H29 VPD4 AH8 H30 ...
Page 60
Signal Definitions (Continued) 2.4.4 CRT/TFT Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA SETRES P2 B15 On-Chip RAMDAC RED K1 B12 GREEN M3 A14 BLUE N2 A15 TFT (External DAC) Interface TFTDCK A22 AA1 J4 A10 TFTDE C16 U3 ...
Page 61
Signal Definitions (Continued) 2.4.5 ACCESS.bus Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA AB2D AL11 M29 2.4.6 PCI Bus Interface Signals BalL No. Signal Name EBGA TEPBGA PCICLK E2 PCICLK0 D3 PCICLK1 E4 AD[31:24] See See Table 2-3 Table ...
Page 62
Signal Definitions (Continued) 2.4.6 PCI Bus Interface Signals (Continued) BalL No. Signal Name EBGA TEPBGA INTA# AE3 D26 INTB# AF1 C26 INTC# H4 INTD# B22 AA2 PAR C10 FRAME# E1 IRDY# C8 www.national.com Type Description I PCI Interrupts. The SC2200 ...
Page 63
Signal Definitions (Continued) 2.4.6 PCI Bus Interface Signals (Continued) BalL No. Signal Name EBGA TEPBGA TRDY# B8 STOP# D9 Revision 3.0 Type Description F1 I/O Target Ready. TRDY# is asserted to indicate that the target agent is able to complete ...
Page 64
Signal Definitions (Continued) 2.4.6 PCI Bus Interface Signals (Continued) BalL No. Signal Name EBGA TEPBGA LOCK# C9 DEVSEL# B5 PERR# B9 www.national.com Type Description H3 I/O Lock Operation. LOCK# indicates an atomic operation that may require multiple transac- tions to ...
Page 65
Signal Definitions (Continued) 2.4.6 PCI Bus Interface Signals (Continued) BalL No. Signal Name EBGA TEPBGA SERR# A9 REQ1# E3 REQ0# C1 GNT1# D2 GNT0# D4 Revision 3.0 Type Description H1 I/O System Error. SERR# can be asserted by any agent ...
Page 66
Signal Definitions (Continued) 2.4.7 Sub-ISA Interface Signals Ball No. Signal Name EBGA TEPBGA A[23:0] See See Table 2-3 Table 2-5 on page on page 32. D15 See See Table 2-3 Table 2-5 D14 on page on page D13 32. D12 ...
Page 67
Signal Definitions (Continued) 2.4.7 Sub-ISA Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA IRQ9 C22 AA3 IOCHRDY H4 2.4.8 Low Pin Count (LPC) Bus Interface Signals Ball No. Signal Name EBGA TEPBGA LAD3 AJ10 L29 LAD2 AK10 L30 LAD1 ...
Page 68
Signal Definitions (Continued) 2.4.9 IDE Interface Signals Ball No. Signal Name EBGA TEPBGA IDE_RST# A22 AA1 IDE_ADDR2 C17 IDE_ADDR1 C26 AE1 IDE_ADDR0 A26 AD3 IDE_DATA[15:0] See See Table 2-3 Table 2-5 on page on page 32. IDE_IOR0# C21 IDE_IOR1# AH3 ...
Page 69
Signal Definitions (Continued) 2.4.9 IDE Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA IRQ14 D25 AF1 IRQ15 H30 AJ8 2.4.10 Universal Serial Bus (USB) Interface Signals Ball No. Signal Name EBGA TEPBGA POWER_EN B28 AH1 OVER_CUR# C27 AF4 DPOS_PORT1 ...
Page 70
Signal Definitions (Continued) 2.4.11 Serial Ports (UARTs) Interface Signals Ball No. Signal Name EBGA TEPBGA SIN1 D26 AG2 SIN2 AJ4 E28 SIN3 J28 AK8 SOUT1 B27 AF3 SOUT2 AK3 D29 SOUT3 J3 C11 RTS2# AH4 C30 CTS2# AJ2 C31 DTR1#/BOUT1 ...
Page 71
Signal Definitions (Continued) 2.4.12 Parallel Port Interface Signals Ball No. Signal Name EBGA TEPBGA ACK# U3 B18 AFD#/DSTRB# AB2 D22 BUSY/WAIT# T1 B17 ERR# AA3 D21 INIT# Y3 B21 PD7 U1 A18 PD6 V3 A20 PD5 V2 C19 PD4 V1 ...
Page 72
Signal Definitions (Continued) 2.4.12 Parallel Port Interface Signals (Continued) Ball No. Signal Name EBGA TEPBGA STB#/WRITE# AB1 A22 2.4.13 Fast Infrared (IR) Port Interface Signals Ball No. Signal Name EBGA TEPBGA IRRX1 J28 AK8 IRRX2/GPIO38 AJ9 K28 IRTX J3 C11 ...
Page 73
Signal Definitions (Continued) 2.4.14 AC97 Audio Interface Signals Ball No. Signal Name EBGA TEPBGA BIT_CLK AL14 U30 SDATA_OUT AK13 P29 SDATA_IN AK14 U31 SDATA_IN2 H31 AL8 SYNC AL13 P30 AC97_CLK AJ14 P31 AC97_RST# AJ15 U29 PC_BEEP AL15 V31 Revision 3.0 ...
Page 74
Signal Definitions (Continued) 2.4.15 Power Management Interface Signals Ball No. Signal Name EBGA TEPBGA CLK32 H29 AH8 GPWIO0 E31 AH6 GPWIO1 G28 AK5 GPWIO2 G29 AJ6 LED# D31 AL4 ONCTL# E30 AJ5 PWRBTN# E29 AH5 PWRCNT1 F31 AK6 PWRCNT2 G31 ...
Page 75
Signal Definitions (Continued) 2.4.16 GPIO Interface Signals Ball No. Signal Name EBGA TEPBGA GPIO0 H1 D11 GPIO1 H2 D10 AL12 N30 GPIO6 AH3 D28 GPIO7 AH4 C30 GPIO8 AJ2 C31 GPIO9 AG4 C28 GPIO10 AJ1 B29 GPIO11 H30 AJ8 GPIO12 ...
Page 76
Signal Definitions (Continued) 2.4.17 Debug Monitoring Interface Signals Ball No. Signal Name EBGA TEPBGA FPCICLK U3 B18 F_AD7 U1 A18 F_AD6 V3 A20 F_AD5 V2 C19 F_AD4 V1 C18 F_AD3 W2 C20 F_AD2 W3 D20 F_AD1 Y1 A21 F_AD0 AA1 ...
Page 77
Signal Definitions (Continued) 2.4.18 JTAG Interface Signals Ball No. Signal Name EBGA TEPBGA TCK AL4 E31 TDI AK5 F29 TDO AH6 E30 TMS AJ5 F28 TRST# AK4 E29 Revision 3.0 Type Description I JTAG Test Clock. This signal has an ...
Page 78
Signal Definitions (Continued) 2.4.19 Test and Measurement Interface Signals Ball No. Signal Name EBGA TEPBGA PLL6B C28 AG4 PLL5B B29 AJ1 PLL2B D28 AH3 GXCLK AL16 V30 TEST3 AL16 V30 TEST2 B29 AJ1 TEST1 C28 AG4 TEST0 D28 AH3 GTEST ...
Page 79
Signal Definitions (Continued) 2.4.20 Power, Ground and No Connections Ball No. Signal Name EBGA AV R3 SSPLL2 AV E28 SSPLL3 V R1 PLL2 V C31 PLL3 AV AF4 CCUSB AV AG1 SSUSB AV L3, M1, N1 CCCRT AV L1, N3, ...
Page 80
General Configuration Block The General Configuration block includes registers for: • Pin Multiplexing and Miscellaneous Configuration • WATCHDOG Timer • High-Resolution Timer • Clock Generators A selectable interrupt is shared by all these functions. 3.1 CONFIGURATION BLOCK ADDRESSES Registers ...
Page 81
General Configuration Block 3.2 MULTIPLEXING, INTERRUPT SELECTION, AND BASE ADDRESS REGISTERS The registers described inTable 3-2 are used to determine general configuration for the SC2200. These registers also indicate which multiplexed signals are issued via balls from Table 3-2. Multiplexing, ...
Page 82
General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 25 AC97CKEN (Enable AC97_CLK Output). This bit enables the output drive of AC97_CLK (EBGA ball AJ14 / TEPBGA ball P31). 0: AC97_CLK output is HiZ. ...
Page 83
General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 23 TFTPP (TFT/Parallel Port). Determines whether certain balls are used for TFT or PP/ACB1/FPCI. This bit is set power-on if the TFT_PRSNT ...
Page 84
General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 21 IOCSEL (Select I/O Commands). Selects ball functions. Ball # 0: I/O Command Signals EBGA / TEPBGA Name IOR# DOCR ...
Page 85
General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 12 TRDESEL (Select TRDE#). Selects ball function. Ball # 0: Sub-ISA Signal EBGA / TEPBGA Name H1 / D11 TRDE# 11 EIDE (Enable IDE Outputs). ...
Page 86
General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 16 Delay HSYNC. HSYNC delay by two TFT clock cycles. 0: There is no delay on HSYNC. 1: HYSNC is delayed twice by rising edge ...
Page 87
General Configuration Block Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued) Bit Description 0 SDBE0 (Slave Disconnect Boundary Enable). Works in conjunction with the GX1 module’s PCI Control Function 2 Regis- ter (Index 41h), bit 1 (SDBE1). Sets ...
Page 88
General Configuration Block 3.3 WATCHDOG The SC2200 includes a WATCHDOG function to serve as a fail-safe mechanism in case the system becomes hung. When triggered, the WATCHDOG mechanism returns the system to a known state by generating an interrupt, an ...
Page 89
General Configuration Block WATCHDOG Interrupt The WATCHDOG interrupt (if configured and enabled) is routed to an IRQ signal. The IRQ signal is programmable via the INTSEL register (Offset 38h, described in Table 3-2 "Multiplexing, Interrupt Selection, and Base Address Regis- ...
Page 90
General Configuration Block Table 3-3. WATCHDOG Registers (Continued) Bit Description Offset 04h This register contains WATCHDOG status information. 7:4 Reserved. Write as read. 3 WDRST (WATCHDOG Reset Asserted) (Read Only) This bit is set to 1 when WATCHDOG Reset is ...
Page 91
General Configuration Block 3.4 HIGH-RESOLUTION TIMER The SC2200 provides an accurate time value that can be used as a time stamp by system software. This time is called the High-Resolution Timer. The length of the timer value can be extended ...
Page 92
General Configuration Block Table 3-4. High-Resolution Timer Registers Bit Description Offset 08h-0Bh This register contains the current value of the High-Resolution Timer. 31:0 Current Timer Value. Offset 0Ch This register supplies the High-Resolution Timer status information. 7:1 Reserved 0 TMSTS ...
Page 93
General Configuration Block 3.5 CLOCK GENERATORS AND PLLS This section describes the registers for the clocks required by the GX1 module, Core Logic module, and the Video Processor, and how these clocks are generated. See Fig- ure 3-2 for a ...
Page 94
General Configuration Block 3.5.1 27 MHz Crystal Oscillator The internal oscillator employs an external crystal con- nected to the on-chip amplifier. The on-chip amplifier is accessible on the X27I input and X27O output signals. See Figure 3-3 for the recommended ...
Page 95
General Configuration Block 3.5.2 GX1 Module Core Clock The core clock is generated by an Analog Delay Loop (ADL) clock generator from the internal Fast-PCI clock. The clock can be any whole-number multiple of the input clock between 4 and ...
Page 96
General Configuration Block 3.5.4 SuperI/O Clocks The SuperI/O module requires a 48 MHz input for Fast infrared (FIR), UART, and other functions. This clock is sup- plied by PLL4 using a multiplier value of 576/(108x3) to generate 48 MHz. 3.5.5 ...
Page 97
General Configuration Block Table 3-8. Clock Generator Configuration (Continued) Bit Description 2 FM1SD (Shut Down PLL4). 0: PLL4 is enabled. 1: PLL4 is shutdown, unless internal Fast-PCI clock is strapped to 48 MHz. 1 C48MD (Disable SuperI/O and USB Clock). ...
Page 98
SuperI/O Module The SuperI/O (SIO) module is a member of National Semi- conductor’s SuperI/O family of integrated PC peripherals PC98 and ACPI compliant SIO that offers a single-cell solution to the most commonly used ISA peripherals. ...
Page 99
SuperI/O Module (Continued) 4.1 FEATURES PC98 and ACPI Compliant • PnP Configuration Register structure • Flexible resource allocation for all logical devices: — Relocatable base address — 9 Parallel IRQ routing options — 3 optional 8-bit DMA channels (where applicable) ...
Page 100
SuperI/O Module (Continued) 4.2 MODULE ARCHITECTURE The SIO module comprises a collection of generic func- tional blocks. Each functional block is described in detail later in this chapter. The beginning of this chapter describes the SIO structure and provides all ...
Page 101
SuperI/O Module (Continued) 4.3 CONFIGURATION STRUCTURE / ACCESS This section describes the structure of the configuration register file, and the method of accessing the configuration registers. 4.3.1 Index-Data Register Pair The SIO configuration access is performed via an Index- Data ...
Page 102
SuperI/O Module (Continued) Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a non- existing register or the LDN is 07h or higher than 08h), are ignored and a read returns 00h on ...
Page 103
SuperI/O Module (Continued) 4.4 STANDARD CONFIGURATION REGISTERS As illustrated in Figure 4-4, the Standard Configuration reg- isters are broadly divided into two categories: SIO Control and Configuration registers and Logical Device Control and Configuration registers (one per logical device, some ...
Page 104
SuperI/O Module (Continued) Table 4-3 provides the bit definitions for the Standard Con- figuration registers. • All reserved bits return 0 on reads, except where noted otherwise. They must not be modified as such modifica- tion may cause unpredictable results. ...
Page 105
SuperI/O Module (Continued) Table 4-3. Standard Configuration Registers Bit Description Index 75h Indicates selected DMA channel for DMA 1 of the logical device (1 - the second DMA channel in case of using more than one DMA channel). 7:3 Reserved. ...
Page 106
SuperI/O Module (Continued) 4.4.1 SIO Control and Configuration Registers Table 4-4 lists the SIO Control and Configuration registers and Table 4-5 provides their bit formats. Table 4-4. SIO Control and Configuration Register Map Index Type Name 20h RO SID. SIO ...
Page 107
SuperI/O Module (Continued) 4.4.2 Logical Device Control and Configuration As described in Section 4.3.2 "Banked Logical Device Reg- isters" on page 101, each functional block is associated with a Logical Device Number (LDN). This section provides the register descriptions for ...
Page 108
SuperI/O Module (Continued) Bit Description Index F0h When any non-reserved bit in this register is set can be cleared only by hardware reset. 7 Block Standard RAM effect on Standard RAM access. (Default) 1: Read ...
Page 109
SuperI/O Module (Continued) 4.4.2.2 LDN 01h - System Wakeup Control Table 4-8 lists registers that are relevant to the configura- tion of System Wakeup Control (SWC). These registers are Index Type Configuration Register or Action 30h R/W Activate. When bit ...
Page 110
SuperI/O Module (Continued) 4.4.2.3 LDN 02h - Infrared Communication Port or Serial Port 3 Table 4-9 lists the configuration registers which affect the Infrared Communication Port or Serial Port 3 (IRCP/SP3). Index Type Configuration Register or Action 30h R/W Activate. ...
Page 111
SuperI/O Module (Continued) 4.4.2.4 LDN 03h and 08h - Serial Ports 1 and 2 Serial Ports 1 and 2 are identical, except for their reset val- ues. Serial Port 1 is designated as LDN 03h and Serial Port 2 as ...
Page 112
SuperI/O Module (Continued) 4.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 2 ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identi- cal. Each ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. ACB1 ...
Page 113
SuperI/O Module (Continued) 4.4.2.6 LDN 07h - Parallel Port The Parallel Port supports all IEEE 1284 standard commu- nication modes: Compatibility (known also as Standard or SPP), Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ...
Page 114
SuperI/O Module (Continued) 4.5 REAL-TIME CLOCK (RTC) The RTC provides timekeeping and calendar management capabilities. The RTC uses a 32.768 KHz signal as the basic clock for timekeeping. It also includes 242 bytes of battery-backed RAM for general-purpose use. The ...
Page 115
SuperI/O Module (Continued) External Elements Choose C and C capacitors (see Figure 4-5 on page 1 2 114) to match the crystal’s load capacitance. The load capacitance C “seen” by crystal Y is comprised series with C ...
Page 116
SuperI/O Module (Continued) 4.5.2.4 Timekeeping Data Format Time is kept in BCD or binary format, as determined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24- hour format, as determined by bit 1 of ...
Page 117
SuperI/O Module (Continued) 4.5.2.6 Power Supply The device is supplied from two supply voltages, as shown in Figure 4-8: • System standby power supply voltage, V • Backup voltage, from low capacity Lithium battery A standby voltage from ...
Page 118
SuperI/O Module (Continued) 4.5.2.7 System Power States The system power state may be No Power, Power On, Power Off or Power Failure. Table 4-18 indicates the power- source combinations for each state. No other power-source combinations are valid. In addition, ...
Page 119
SuperI/O Module (Continued) 4.5.2.9 Interrupt Handling The RTC has a single Interrupt Request line which handles the following three interrupt conditions: • Periodic interrupt. • Alarm interrupt. • Update end interrupt. The interrupts are generated if the respective enable bits ...
Page 120
SuperI/O Module (Continued) 4.5.3 RTC Registers The RTC registers can be accessed (see Section 4.4.2.1 "LDN 00h - Real-Time Clock" on page 107) at any time dur- ing normal operation mode (i.e.,when V ommended operation range). This access is disabled ...
Page 121
SuperI/O Module (Continued) Bit Description Index 00h 7:0 Seconds Data. Values may BCD format binary format. Index 01h 7:0 Seconds Alarm Data. Values may BCD ...
Page 122
SuperI/O Module (Continued) Bit Description 5 Alarm Interrupt. This interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and month time equal their respective alarm counterparts cleared long as ...
Page 123
SuperI/O Module (Continued) Bit Description Index Programmable 7:0 Month Alarm Data. Values may BCD format Binary format. When bits 7 and 6 are both set to one (“11”), unconditional match ...
Page 124
SuperI/O Module (Continued) Parameter Seconds Minutes Hours 12-hour mode: 24-hour mode: Day (Sunday = 01) Date Month (January = 01) Year Century ...
Page 125
SuperI/O Module (Continued) 4.6 SYSTEM WAKEUP CONTROL (SWC) The SWC wakes up the system by sending a power-up request to the ACPI controller in response to the following maskable system events: • Modem ring (RI2#) • Audio Codec event (SDATA_IN2) ...
Page 126
SuperI/O Module (Continued) 4.6.2 SWC Registers The SWC registers are organized in two banks. The offsets are related to a base address that is determined by the SWC Base Address Register in the logical device configu- ration. The lower three ...
Page 127
SuperI/O Module (Continued) Table 4-29. Banks 0 and 1 - Common Control and Status Registers Bit Description Offset 00h This register is set to 00h on power- 5.2.9.4 "Power Management Events" on page 169.) 7 Reserved. 6 Reserved. ...
Page 128
SuperI/O Module (Continued) Table 4-30. Bank 1 - CEIR Wakeup Configuration and Control Registers Bit Description Bank 1, Offset 03h This register is set to 00h on power- 7:6 Reserved. 5:4 CEIR Protocol Select. 00: RC5 01: NEC/RCA ...
Page 129
SuperI/O Module (Continued) Table 4-30. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued) Bit Description These two registers (IRWTR1L and IRWTR1H) define the low and high limits of time range 1 (see Table 4-26 on page 125). The ...
Page 130
SuperI/O Module (Continued) 4.7 ACCESS.BUS INTERFACE The SC2200 has two ACCESS.bus (ACB) controllers. ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer, Intel's SMBus, and Philips’ The ACB can be configured as a ...
Page 131
SuperI/O Module (Continued) 4.7.3 Acknowledge (ACK) Cycle The ACK cycle consists of two signals: the ACK clock pulse sent by the master with each byte transferred, and the ACK signal sent by the receiving device (see Figure 4-15). The master ...
Page 132
SuperI/O Module (Continued) 4.7.4 Acknowledge After Every Byte Rule According to this rule, the master generates an acknowl- edge clock pulse after each byte transfer, and the receiver sends an acknowledge signal after every byte received. There are two exceptions ...
Page 133
SuperI/O Module (Continued) Sending the Address Byte When the device is the active master of the ACCESS.bus (ACBST[1] is set), it can send the address on the bus. The address sent should not be the device’s own address, as defined ...
Page 134
SuperI/O Module (Continued) Master Error Detection The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer, or the acknowledge cycle) and a conflict on the data lines of the ACCESS.bus ...
Page 135
SuperI/O Module (Continued) 4.7.10 ACB Registers Each functional block is associated with a Logical Device Number (LDN) (see Section 4.3.2 "Banked Logical Device Registers" on page 101). ACCESS.Bus Port 1 is assigned Offset Type 00h R/W 01h R/W 02h R/W ...
Page 136
SuperI/O Module (Continued) Bit Description 1 MASTER. (RO) 0: Arbitration loss (BER, bit 5, is set) or recognition of a Stop Condition. 1: Bus master request succeeded and master mode active. 0 XMIT (Transmit). (RO) Direction bit. 0: Master/slave transmit ...
Page 137
SuperI/O Module (Continued) Bit Description 2 INTEN (Interrupt Enable). 0: ACB interrupt disabled. 1: ACB interrupt enabled. An interrupt is generated in response to one of the following events: -Detection of an address match (ACBST[ and ACBCTL1[6] = ...
Page 138
SuperI/O Module (Continued) 4.8 LEGACY FUNCTIONAL BLOCKS This section briefly describes the following blocks that pro- vide legacy device functions: • Parallel Port. • Serial Port 1 and Serial Port 2 (SP1 and SP2), UART functionality for both SP1 and ...
Page 139
SuperI/O Module (Continued) Table 4-35. Parallel Port Bit Map for First Level Offset Offset Name 7 000h DATAR AFIFO 001h DSR Printer Status 002h DCR RSVD 003h ADDR 004h DATA0 005h DATA1 006h DATA2 007h DATA3 400h CFIFO 400h DFIFO ...
Page 140
SuperI/O Module (Continued) 4.8.2 UART Functionality (SP1 and SP2) Both SP1 and SP2 provide UART functionality. The generic SP1 and SP2 support serial data communication with remote peripheral device or modem using a wired inter- face. The functional blocks can ...
Page 141
SuperI/O Module (Continued Offset Type 00h R/W 01h R/W 02h --- 03h W R/W 04h-07h --- 1. When bit ...
Page 142
SuperI/O Module (Continued) Register Offset Name 7 00h RXD TXD 01h 1 IER RSVD 2 IER 02h 1 FEN[1:0] EIR 2 RSVD EIR FCR RXFTH[1:0] 03h 5 BKSE LCR 5 BKSE BSR 04h 1 MCR 2 MCR 05h LSR ER_INF ...
Page 143
SuperI/O Module (Continued) Register Offset Name 7 00h BGD(L) 01h BGD(H) 02h EXCR1 BTEST 03h BSR BKSE 04h EXCR2 LOCK 05h RSVD 06h RXFLV 07h TXFLV Register Offset Name 7 00h MRID 01h SH_LCR BKSE 02h SH_FCR RXFTH[1:0] 03h BSR ...
Page 144
SuperI/O Module (Continued) 4.8.3 IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality This section describes the IRCP/SP3 support registers. The IRCP/SP3 functional block provides advanced, versa- tile serial communications features with IR capabilities. The IRCP/SP3 also supports two ...
Page 145
SuperI/O Module (Continued) BSR Bits ...
Page 146
SuperI/O Module (Continued) Offset Type 00h RO 01h RO 02h RO 03h R/W 04h-07h --- Offset Type 00h RO 01h RO 02h R/W 03h R/W 04h R/W RO 05h R/W RO 06h R/W RO 07h R/W RO Offset Type 00h ...
Page 147
SuperI/O Module (Continued) Offset Type 00h R/W 01h R/W 02h R/W 03h R/W 04h R/W 05h-07h --- Offset Type 00h R/W 01h R/W 02h R/W 03h R/W 04h R/W 05h-06h --- 07h R/W Register Offset Name 7 00h RXD TXD ...
Page 148
SuperI/O Module (Continued) Register Offset Name 7 00h LBGD(L) 01h LBGD(H) 02h RSVD 03h LCR BKSE BSR BKSE 04h-07h RSVD Register Offset Name 7 00h BGD(L) 01h BGD(H) 02h EXCR1 BTEST 03h BSR BKSE 04h EXCR2 LOCK 05h RSVD 06h ...
Page 149
SuperI/O Module (Continued) Register Offset Name 7 06h RFRML(L)/ RFRCC(L) 07h RFRML(H)/ RFRCC(H) Register Offset Name 7 00h SPR2 01h SPR3 02h RSVD 03h BSR BKSE 04h IRCR2 RSVD 05h FRM_ST VLD 06h RFRL(L)/ LSTFRC 07h RFRL(H) Register Offset Name ...
Page 150
Core Logic Module The Core Logic module is an enhanced PCI-to-Sub-ISA bridge (South Bridge), this module is ACPI-compliant, and provides AT/Sub-ISA functionality. The Core Logic module also contains state-of-the-art power management. Two bus mastering IDE controllers are included for ...
Page 151
Core Logic Module (Continued) 5.2 MODULE ARCHITECTURE The Core Logic architecture provides the internal functional blocks shown in Figure 5-1. • Fast-PCI interface to external PCI bus • IDE controllers (UDMA-33) • USB controllers • Sub-ISA bus interface UDMA33 IDE ...
Page 152
Core Logic Module (Continued) 5.2.1 Fast-PCI Interface to External PCI Bus The Core Logic module provides a PCI bus interface that is both a slave for PCI cycles initiated by the GX1 module or other PCI master devices, and a ...
Page 153
Core Logic Module (Continued) 5.2.3 IDE Controller The Core Logic module integrates a PCI bus mastering, ATA-4 compatible IDE controller. This controller supports UltraDMA, Multiword DMA and Programmed I/O (PIO) modes. Two devices are supported on the IDE controller. The ...
Page 154
Core Logic Module (Continued) 5.2.3.3 Bus Master Mode Two IDE bus masters are provided to perform the data transfers for the primary and secondary channels. The IDE controller of the Core Logic module off-loads the CPU and improves system performance ...
Page 155
Core Logic Module (Continued) 5.2.3.4 UltraDMA/33 Mode The IDE controller of the Core Logic module supports UltraDMA/33. It utilizes the standard IDE Bus Master func- tionality to interface, initiate and control the transfer. UltraDMA/33 definition also incorporates a Cyclic Redun- ...
Page 156
Core Logic Module (Continued) 5.2.4 Universal Serial Bus The Core Logic module provides three complete, indepen- dent USB ports. Each port has a Data "Negative" and a Data "Positive" signal. The USB ports are Open Host Controller Interface (Open- HCI) ...
Page 157
Core Logic Module (Continued) 5.2.5.1 Sub-ISA Bus Cycles The ISA bus controller issues multiple ISA cycles to satisfy PCI transactions that are larger than 16 bits. A full 32-bit read or write results in two 16-bit ISA transactions or four ...
Page 158
Core Logic Module (Continued) REQ# GNT# FRAME# Fast-PCI IRDY# TRDY# STOP# BALE ISA RD#, IOR GX1 transaction 2 - IDE bus master - starts and completes 3 - End of ISA cycle Figure 5-3. PCI to ISA Cycles ...
Page 159
Core Logic Module (Continued) 5.2.5.5 ISA DMA DMA transfers occur between ISA I/O peripherals and sys- tem memory (i.e., not available externally). The data width can be either bits. Out of the seven DMA channels available, four ...
Page 160
Core Logic Module (Continued) 5.2.5.6 ROM Interface The Core Logic module positively decodes memory addresses 000F0000h-000FFFFFh FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory cycles cause the Core Logic module to claim the cycle, and generate an ISA bus memory cycle ...
Page 161
Core Logic Module (Continued) PCI FRAME# TRDY#, IRDY# GNT[x] ROMCS#, DOCCS#, IOCS0#, IOCS1# PAR, DEVSEL#,STOP# AD[31:0], C/BE[3:0]# Figure 5-6. PCI Change to Sub-ISA and Back 5.2.6 AT Compatibility Logic The Core Logic module integrates: • Two 8237-equivalent DMA controllers with ...
Page 162
Core Logic Module (Continued) In block transfer mode, the DMA controller executes all of its transfers consecutively without releasing the PCI bus. In demand transfer mode, DMA transfer cycles continue to occur as long as DRQ is high or terminal ...
Page 163
Core Logic Module (Continued) DMA Page Registers and Extended Addressing The DMA Page registers provide the upper address bits during DMA cycles. DMA addresses do not increment or decrement across page boundaries. Page boundaries for the 8-bit channels (Channels 0 ...
Page 164
Core Logic Module (Continued) 5.2.6.3 Programmable Interrupt Controller The Core Logic module contains two 8259A-equivalent programmable interrupt controllers, with eight interrupt request lines each, for a total of 16 interrupts. The two con- trollers are cascaded internally, and two of ...
Page 165
Core Logic Module (Continued) PIC Interrupt Sequence A typical AT-compatible interrupt sequence is as follows. Any unmasked interrupt generates the internal INTR signal to the CPU. The interrupt controller then responds to the interrupt acknowledge (INTA) cycles from the CPU. ...
Page 166
Core Logic Module (Continued) The assertion of a fast keyboard reset (WM_RST SMI) is controlled by bit 0 in I/O Port 092h or by monitoring for the keyboard command sequence (write data = FEh to I/O port 64h). If bit ...
Page 167
Core Logic Module (Continued) 5.2.9 Power Management Logic The Core Logic module integrates advanced power man- agement features including idle timers for common system peripherals, address trap registers for programmable address ranges for I/O or memory accesses, four program- mable ...
Page 168
Core Logic Module (Continued) SL1 Sleep State (ACPI S1) In this state the core processor Suspend mode (all its clocks are stopped, including the memory controller and the display controller). The SDRAM is placed in self-refresh mode. ...
Page 169
Core Logic Module (Continued) 5.2.9.3 Power Planes Control The SC2200 supports up to three power planes. Three sig- nals are used to control these power planes. Table 5-6 describes the signals and when each is asserted. Table 5-6. Power Planes ...
Page 170
Core Logic Module (Continued) will remain active after POR#. Therefore, BIOS must ensure that ACPI is inactive before GPIO63 is pulsed low. Power Button Wake Event - Detection of a high-to-low transition on the debounced PWRBTN# input signal when in ...
Page 171
Core Logic Module (Continued) 5.2.10.2 CPU Power Management The three greatest power consumers in a system are the display, the hard drive, and the CPU. The power manage- ment of the first two is relatively straightforward and is dis- cussed ...
Page 172
Core Logic Module (Continued) 3 Volt Suspend The Core Logic module supports the stopping of the CPU and system clocks for a 3V Suspend state. If appropriately configured, via the Clock Stop Control register (F0 Index BCh), the Core Logic ...
Page 173
Core Logic Module (Continued) General Purpose Timers The Core Logic module contains two general purpose idle timers, General Purpose Timer 1 (F0 Index 88h) and Gen- eral Purpose Timer 2 (F0 Index 8Ah). These two timers are similar to the ...
Page 174
Core Logic Module (Continued) SMI# Asserted If Bit (External SMI) GX1 Module Core Logic Module F1BAR0+I/O Offset 02h Read to Clear to determine top-level source of SMI Bits [15:10] Other_SMI Bit 9 GTMR_TRP_SMI Bits [8:0] Other_SMI Top ...
Page 175
Core Logic Module (Continued) 5.2.10.4 Power Management Programming Summary Table 5-9 provides a programming register summary for the power management timers, traps, and functions. For com- Table 5-9. Device Power Management Programming Summary Device Power Management Resource Global Timer Enable ...
Page 176
Core Logic Module (Continued) 5.2.11 GPIO Interface GPIOs in the in the Core Logic module are pro- vided for system control. For further information, see Sec- tion 3.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page ...
Page 177
Core Logic Module (Continued) Physical Region Descriptor Table Address Before the bus master starts a master transfer it must be pro- grammed with a pointer (PRD Table Address register Physical Region Descriptor Table. This pointer sets the start- ...
Page 178
Core Logic Module (Continued) 4) Read the SMI Status register to clear the Bus Master Error and End of Page bits (bits 1 and 0). Set the correct direction to the Read or Write Control bit (Command register bit 3). ...
Page 179
Core Logic Module (Continued) 5.2.12.2 AC97 Codec Interface The AC97 codec (e.g., LM4548) is the master of the serial interface and generates the clocks to Core Logic module. Figure 5-13 shows the signal connections between two codecs and the SC2200: ...
Page 180
Core Logic Module (Continued) 5.2.12.3 VSA Technology Support Hardware The Core Logic module incorporates the required hard- ware in order to support the Virtual System Architecture (VSA™) technology for capture and playback of audio using an external codec. This eliminates ...
Page 181
Core Logic Module (Continued) Fast Path Write captures the data and address bit 1 (A1) of the first access, but does not generate an SMI stored in F3BAR0+Memory Offset 14h[15]. The second access causes an SMI, and the ...
Page 182
Core Logic Module (Continued) 5.2.12.4 IRQ Configuration Registers The Core Logic module provides the ability to set and clear IRQs internally through software control. If the IRQs are configured for software control, they do not respond to external hardware. There ...
Page 183
Core Logic Module (Continued) 5.2.12.6 LPC Interface Signal Definitions The LPC specification lists seven required and six optional signals for supporting the LPC interface. Many of the sig- nals are the same signals found on the PCI interface and do ...
Page 184
Core Logic Module (Continued) 5.3 REGISTER DESCRIPTIONS The Core Logic module is a multi-function module. Its reg- ister space can be broadly divided into three categories in which specific types of registers are located: 1) Chipset Register Space (F0-F5) (Note ...
Page 185
Core Logic Module (Continued) 5.3.2 Register Summary The tables in this subsection summarize the registers of the Core Logic module. Included in the tables are the regis- ter’s reset values and page references where the bit for- mats are found. ...
Page 186
Core Logic Module (Continued) Table 5-14. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support Summary (Continued) Width F0 Index (Bits) Type Name 70h-71h 16 R/W IOCS1# Base Address Register 72h 8 R/W IOCS1# Control Register 73h ...
Page 187
Core Logic Module (Continued) Table 5-14. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support Summary (Continued) Width F0 Index (Bits) Type Name BAh 8 RO PIT Shadow Register BBh 8 RO RTC Index Shadow Register BCh ...
Page 188
Core Logic Module (Continued) Table 5-15. F0BAR0: GPIO Support Registers Summary F0BAR0+ Width I/O Offset (Bits) Type Name 00h-03h 32 R/W GPDO0 — GPIO Data Out 0 Register 04h-07h 32 RO GPDI0 — GPIO Data In 0 Register 08h-0Bh 32 ...
Page 189
Core Logic Module (Continued) Table 5-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary Width F1 Index (Bits) Type Name 00h-01h 16 RO Vendor Identification Register 02h-03h 16 RO Device Identification Register 04h-05h 16 R/W PCI Command ...
Page 190
Core Logic Module (Continued) Table 5-19. F1BAR1: ACPI Support Registers Summary F1BAR1+ Width I/O Offset (Bits) Type Name 00h-03h 32 R/W P_CNT — Processor Control Register 04h 8 RO Reserved, do not read 05h 8 RO P_LVL3 — Enter C3 ...
Page 191
Core Logic Module (Continued) Table 5-20. F2: PCI Header Registers for IDE Controller Support Summary Width F2 Index (Bits) Type Name 00h-01h 16 RO Vendor Identification Register 02h-03h 16 RO Device Identification Register 04h-05h 16 R/W PCI Command Register 06h-07h ...
Page 192
Core Logic Module (Continued) Table 5-21. F2BAR4: IDE Controller Support Registers Summary F2BAR4+ Width I/O Offset (Bits) Type 00h 8 R/W IDE Bus Master 0 Command Register — Primary 01h --- --- Not Used 02h 8 R/W IDE Bus Master ...
Page 193
Core Logic Module (Continued) Table 5-23. F3BAR0: XpressAUDIO Support Registers Summary F3BAR0+ Memory Width Offset (Bits) Type Name 00h-03h 32 R/W Codec GPIO Status Register 04h-07h 32 R/W Codec GPIO Control Register 08h-0Bh 32 R/W Codec Status Register 0Ch-0Fh 32 ...
Page 194
Core Logic Module (Continued) Table 5-24. F5: PCI Header Registers for X-Bus Expansion Support Summary Width F5 Index (Bits) Type Name 00h-01h 16 RO Vendor Identification Register 02h-03h 16 RO Device Identification Register 04h-05h 16 R/W PCI Command Register 06h-07h ...
Page 195
Core Logic Module (Continued) Table 5-26. PCIUSB: USB PCI Configuration Register Summary PCIUSB Width Index (Bits) Type Name 00h-01h 16 RO Vendor Identification 02h-03h 16 RO Device Identification 04h-05h 16 R/W Command Register 06h-07h 16 R/W Status Register 08h 8 ...
Page 196
Core Logic Module (Continued) Table 5-27. USB_BAR: USB Controller Registers Summary USB_BAR0 +Memory Width Offset (Bits) Type Name 00h-03h 32 R/W HcRevision 04h-07h 32 R/W HcControl 08h-0Bh 32 R/W HcCommandStatus 0Ch-0Fh 32 R/W HcInterruptStatus 10h-13h 32 R/W HcInterruptEnable 14h-17h 32 ...
Page 197
Core Logic Module (Continued) Table 5-28. ISA Legacy I/O Register Summary I/O Port Type Name DMA Channel Control Registers (Table 5-43) 000h R/W DMA Channel 0 Address Register 001h R/W DMA Channel 0 Transfer Count Register 002h R/W DMA Channel ...
Page 198
Core Logic Module (Continued) Table 5-28. ISA Legacy I/O Register Summary (Continued) I/O Port Type Name 489h R/W DMA Channel 6 High Page Register 48Ah R/W DMA Channel 7 High Page Register 48Bh R/W DMA Channel 5 High Page Register ...
Page 199
Core Logic Module (Continued) 5.4 CHIPSET REGISTER SPACE The Chipset Register Space of the Core Logic module is comprised of six separate functions (F0-F5), each with its own register space. Base Address Registers (BARs) in each PCI header register space ...
Page 200
Core Logic Module (Continued) Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description 4 Memory Write and Invalidate. Allow the Core Logic module to do memory write and invalidate cycles, if the ...