AD9849KST Analog Devices, AD9849KST Datasheet
AD9849KST
Available stocks
Related parts for AD9849KST
AD9849KST Summary of contents
Page 1
... RG 4 H1–H4 AD9848/AD9849 PxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc. PRODUCT DESCRIPTION The AD9848 and AD9849 are highly integrated CCD signal pro- cessors for digital still camera applications. Both include a complete analog front end with A/D conversion, combined with a program- mable timing driver ...
Page 2
AD9848/AD9849 –TARGET SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE AD9848 AD9849 POWER SUPPLY VOLTAGE, AD9848 Analog (AVDD1 Digital1 (DVDD1) H1–H4 Digital2 (DVDD2) RG Digital3 (DVDD3) D0–D11 Digital4 (DVDD4) All Other Digital POWER SUPPLY VOLTAGE, ...
Page 3
DIGITAL SPECIFICATIONS Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage ...
Page 4
AD9848/AD9849 AD9848–ANALOG SPECIFICATIONS Parameter CDS Gain 1 Allowable CCD Reset Transient 1 Max Input Range Before Saturation 1 Max CCD Black Pixel Amplitude PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range ...
Page 5
AD9849–ANALOG SPECIFICATIONS Parameter CDS Gain 1 Allowable CCD Reset Transient 1 Max Input Range Before Saturation 1 Max CCD Black Pixel Amplitude PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min ...
Page 6
AD9848/AD9849 TIMING SPECIFICATIONS Parameter MASTER CLOCK (CLI), AD9848 CLI Clock Period CLI High/Low Pulsewidth Delay From CLI to Internal Pixel Period Position MASTER CLOCK (CLI), AD9849 CLI Clock Period CLI High/Low Pulsewidth EXTERNAL MODE CLAMPING CLPDM Pulsewidth 1 CLPOB Pulsewidth ...
Page 7
... LQFP Package = 92°C JA Model AD9848KST AD9849KST CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9848/AD9849 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
Page 8
AD9848/AD9849 (LSB PIN IDENTIFIER AD9848 DVSS3 6 TOP VIEW DVDD3 7 (Not to Scale ...
Page 9
EQUIVALENT INPUT/OUTPUT CIRCUITS AVDD2 R AVSS2 AVDD1 330 25k CLI 1.4V AVSS1 DVDD4 DATA THREE- STATE DVSS4 AVSS2 DATA ENABLE DVDD3 DOUT DVSS3 AD9848/AD9849 DVDD4 330 DVSS4 DVDD1 OUTPUT DVSS1 ...
Page 10
AD9848/AD9849 —Typical Linearity and Noise Performance Characteristics 0.50 0.25 0 –0.25 –0.50 0 400 200 600 400 200 600 VGA GAIN CODE – LSB 0.5 0.25 0 –0.25 –0.5 0 500 800 1000 15 ...
Page 11
SYSTEM OVERVIEW V-DRIVER V1–V4, VSG1–VSG8, SUBCK H1–H4, RG CCDIN AD9848/AD9849 CCD INTEGRATED AFE+TD SERIAL INTERFACE Figure 1a and 1b show the typical system application diagrams for the AD9848/AD9849. The CCD output is processed by the AD9848/AD9849’s AFE circuitry, which consists ...
Page 12
AD9848/AD9849 SERIAL INTERFACE TIMING SDATA SCK NOTES 1. SDATA BITS ARE LATCHED ON SCK RISING EDGES SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS. 3. ...
Page 13
Notes about Accessing a Double-Wide Register There are many double-wide registers in the AD9848/AD9849, for example: oprmode, clpdmtog1_0, clpdmscp3, etc. These regis- ters are configured into two consecutive 6-bit registers with the least significant six bits located in the lower ...
Page 14
AD9848/AD9849 Bit Default Address Content Width Value CLPDM [5: [5: [5: [5: [ ...
Page 15
Bit Default Address Content Width Value CLPOB [5: [5: [5: [5: [ ...
Page 16
AD9848/AD9849 Bit Default Address Content Width Value HBLK [5: [5: [5: [5: ...
Page 17
Bit Default Address Content Width Value PBLK [5: [5: [5: [5: [ ...
Page 18
AD9848/AD9849 Bit Default Address Content Width Value AFE REGISTER BREAKDOWN oprmode [7:0] 8'h0 [1:0] 2'h0 2'h1 2'h2 2'h3 [2] [3] [4] [5] [6] [7] ctlmode [5:0] 6'h0 [2:0] 3'h0 3'h1 3'h2 3'h3 3'h4 3'h5 3'h6 3'h7 [3] [4] 1'h0 1'h1 ...
Page 19
PRECISION TIMING HIGH-SPEED TIMING GENERATION The AD9848 and AD9849 generate flexible high-speed timing signals using the Precision Timing core. This core is the founda- tion for generating the timing used for both the CCD and the AFE; the reset gate ...
Page 20
AD9848/AD9849 H-Driver and RG Outputs In addition to the programmable timing positions, the AD9848/ AD9849 features on-chip output drivers for the RG and H1–H4 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver current can ...
Page 21
RISE H1/H3 H2/ FIXED CROSSOVER VOLTAGE P[12] P[0] CLI 1 PIXEL PERIOD t OD DOUT NOTES 1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN 1 CLOCK PERIOD, THE DATA ...
Page 22
AD9848/AD9849 HORIZONTAL CLAMPING AND BLANKING The AD9848/AD9849’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. As with the vertical timing generation, individual sequences are defined for each signal, which are then organized into multiple ...
Page 23
Horizontal Sequence Control The AD9848/AD9849 uses Sequence Change Positions (SCP) and Sequence Pointers (SPTR) to organize the individual horizon- tal sequences four SCPs are available to divide the readout into four separate regions, as shown in Figure 12. ...
Page 24
AD9848/AD9849 H-Counter Synchronization The H-Counter reset occurs on the sixth CLI rising edge fol- lowing the HD falling edge. The PxGA steering is synchronized with the reset of the internal H-Counter. (See Figure 13.) VD 3ns MIN HD 3ns MIN ...
Page 25
POWER-UP PROCEDURE VDD (INPUT) CLI (INPUT) t PWR SERIAL WRITES VD (OUTPUT) HD (OUTPUT) H2/H4 DIGITAL H1/H3, RG OUTPUTS Recommended Power-Up Sequence When the AD9848 and AD9849 are powered up, the following sequence is recommended (refer to Figure 14 for ...
Page 26
AD9848/AD9849 ANALOG FRONT END DESCRIPTION AND OPERATION The AD9848/AD9849 signal processing chain is shown in Figure 15. Each processing step is essential in achieving a high- quality image from the raw CCD pixel data. DC Restore To reduce the large ...
Page 27
ODD FIELD FLD VD HD PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO "0101" LINE FALLING EDGES WILL ALTERNATE THE PxGA GAIN ...
Page 28
AD9848/AD9849 FLD VD HD PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO "012012" LINE FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN ...
Page 29
VD COLOR 3 PxGA STEERING HD STEERING CONTROL SELECTION SHP/SHD 2 GAIN0 GAIN1 4:1 MUX GAIN2 6 GAIN3 PxGA VGA CDS CCD: PROGRESSIVE BAYER MOSAIC SEPARATE COLOR STEERING MODE LINE0 GAIN0, GAIN1, GAIN0, GAIN1... Gb B ...
Page 30
AD9848/AD9849 Optical Black Clamp The optical black clamp loop is used to remove residual offsets in the signal chain and to track low-frequency variations in the CCD’s black level. During the optical black (shielded) pixel interval on each line, the ...
Page 31
APPLICATIONS INFORMATION External Circuit Configuration The AD9848/AD9849 recommended circuit configuration for External Mode is shown in Figure 21. All signals should be carefully routed on the PCB to maintain low noise performance. The CCD output signal should be connected to ...
Page 32
AD9848/AD9849 Driving the CLI Input The AD9848/AD9849’s master clock input (CLI) may be used in two different configurations, depending on the appli- cation. Figure 23a shows a typical dc-coupled input from the master clock source. When the dc-coupled technique is ...
Page 33
TIMING EXAMPLES FOR DIFFERENT SEQUENCES 28 VERT SHIFT DUMMY CCDIN INVALID PIXELS SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM EFF. PIXELS OPTICAL BLACK VERT SHIFT DUMMY CCDIN SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM 2 SEQUENCE 2 V ...
Page 34
AD9848/AD9849 EFF. PIXELS OPTICAL BLACK VERT SHIFT DUMMY CCDIN SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM OB EFFECTIVE PIXELS OPTICAL BLACK VERT SHIFT ...
Page 35
OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75 0.018 (0.45 TOP VIEW (PINS DOWN) COPLANARITY 12 25 0.003 (0.08 MIN 0.019 ...
Page 36
...