AD6600 Analog Devices, AD6600 Datasheet
AD6600
Specifications of AD6600
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AD6600 Summary of contents
Page 1
... In single-channel mode, the full clock rate of 20 MSPS may be applied to a single carrier. The AD6600 may be used as a stand-alone sampling chip may be combined with the AD6620 Digital Receive Signal Pro- cessor. The AD6620 provides 10 dB– additional pro- cessing gain before passing data to a fixed- or floating-point DSP ...
Page 2
... Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs. 3 Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations. 4 Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details. 5 A_SEL and B_SEL should be tied directly to ground or AVCC. 6 Maximum power consumption is computed as maximum current at nominal supplies ...
Page 3
... Output Risetime (D10:D0, RSSI2:0) Output Falltime (D10:D0, RSSI2:0) Output Risetime (AB_OUT) Output Falltime (AB_OUT) NOTES 1 See AD6600 Timing Diagrams. All switching specifications tested by driving ENC and ENC differentially Several timing specifications are a function of Encode high time, t should be kept as close to 50% as possible. ...
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... ENCODE to AB_OUT Falling Low Delay ENCODE to AB_OUT Delay (Setup) @ Encode = 13 MSPS, 50% Duty Cycle @ Encode = 20 MSPS, 50% Duty Cycle NOTES 1 See AD6600 Timing Diagrams. 2 All switching specifications tested by driving ENC and ENC differentially. 3 This specification IS NOT a function of Encode period and duty cycle. 4 This specification IS a function of Encode period and duty cycle. ...
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... AD6600 Unit MHz V p-p V p-p V p-p V p-p Ω Ω Ω Ω Ω Ω Ω Ω dBm dBm dBm dBm Degree Degree dB µV rms µ ...
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... Full V Full V Full V Full V Full V Full V 25° Full V 25° Full V Full V Full V Full V Full V Full IV 28 AD6600AST Typ Max Unit 57 ± 53 ± dBc 68 dBc 68 ± 6 dBc 60 dBc 59 dBc 67 ± ...
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... NOTES 1 AIN, AIN/BIN, BIN: The AD6600 analog inputs are unconditionally stable and guarantee proper operation over the 70 MHz–250 MHz specified operating range. Circuit board layout is critical on this device, and proper PCB layout must be employed to achieve specified results. 2 Analog Input 3 dB Bandwidth is determined by internal track-and-hold ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6600 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom- mended to avoid performance degradation or loss of functionality ...
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... DVCC PIN 1 2 GND IDENTIFIER AVCC GND 5 AD6600 6 RSSI2 TOP VIEW (Not to Scale) 7 RSSI1 8 RSSI0 9 B_SEL 10 A_SEL 11 AIN AD6600 33 DVCC 32 GND 31 AVCC 30 GND 29 AB_OUT 28 CLK2 27 ENC 26 ENC 25 AVCC 24 GND 23 BIN ...
Page 10
... Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Attenuator 3OIP The third order intercept point of the front end of the AD6600 the point at which the third order products would theoreti- cally intercept the input signal level if the input level could increase without bounds ...
Page 11
... Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc. AD6600 TRANSFER FUNCTION ...
Page 12
... AD6600 EQUIVALENT CIRCUITS ATTENUATOR STAGE AVCC EQUIVALENT INPUT R SHOWN ONLY AIN 100 V REF GND BUF AVCC 100 AIN GND AVCC ISEL_A ISEL_B AVCC A_SEL BIAS GND GND DVCC CURRENT MIRROR DVCC V REF 500 CURRENT MIRROR AVCC GND 4 /8 GAIN STAGE FROM ...
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... AD6600 TIMING DIAGRAMS t ENCH ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 1_DRL D [10:0] RSSI [2:0] AB_OUT t ENCH ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 2 D [10:0] RSSI [2:0] AB_OUT t ENCH ENCODE ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 EN_DRL D [10:0] RSSI [2:0] t EN_ARL AB_OUT t ENCL ...
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... AD6600 t ENCH ENCODE ENCODE t CR1 t t CF1 CLK2 L CLK2 CLK2 2 t H_DEN D [10:0] RSSI [2:0] t H_AEN AB_OUT CLK2 D [10:0] RSSI [2:0] AB_OUT 20 ENCODE 40 CLK2 ENCODE 8 CLK2 t ENCL ENCODE t t CR2 CLK2 CF2 CLK2 L CLK2 H2 CLK2 1 CLK2 2 t S_DEN t S_AEN 3 2 ...
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... As shown in Fig- ure 16, at the lowest input levels SNR increases 1 dB for increase in input power. In this range, the AD6600 is set for maximum gain. However, when the input signal level reaches the gain-ranging section (approximately –42 dBFS), the SNR is contained between about 50 dB and between 44 dB and 56 dB including the effects of hysteresis ...
Page 16
... IF frequency recommended is higher than this. The minimum specified frequency is 70 MHz. Since the RSSI control loop is performed on a sample-by-sample basis, the AD6600 very accurately follows the signals into and out of a deep fade. Hysteresis The AD6600 employs hysteresis to prevent the gain-ranging from unnecessarily changing when the signal envelope is near an RSSI threshold ...
Page 17
... AD6600 to approximately 0.8 V p-p differential. This Attenuation helps prevent the larger voltage swings of the clock from feeding or Gain (dB) through to other portions of the AD6600, and limits the noise –12 presented to the encode inputs. A crystal clock oscillator can –6 also be used to drive the RF transformer if an appropriate limiting resistor (typically 100 Ω ...
Page 18
... The recommended method to drive the analog input port is shown in Figure 20. The AD6600 input is actually designed to match easily to a SAW filter such as SAWTEK 855297. This allows the SAW filter to be used in a differential mode, which often improves the operations of a SAW filter ...
Page 19
... Note that AVCC must be held within Volts; how- ever, the DVCC supply may be varied according to output digital logic family. The AD6600 is specified for DVCC = 3 this is a common supply for digital ASICS. Output Loading Care must be taken when designing the data receivers for the AD6600 ...
Page 20
... The two analog inputs are connected via SMA connectors AIN and BIN, which are transformer-coupled to the AD6600 inputs. The transformers have a turns-ratio of 1:4 to match the input resistance of the AD6600 (200 Ω Ω at the SMA connectors. Item Quantity ...
Page 21
... BIN D0 D1 GND D2 AVCC D3 GND D4 AVCC D5 FLT FLT D6 D7 AVCC D8 AVCC D9 GND D10 AIN (MSB) AD6600 GND VCC GND VCC VCC VCC GND ...
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... AD6600 ...
Page 23
... CLK2 D [10:0] RSSI [2:0] AB_OUT Figure 32 shows the timing details between the AD6600 and the AD6620. On Clock 1, D[10:0], RSSI[2:0], and AB_OUT are captured by the AD6620. Since AB_OUT has changed state from the previous clock, the D[10:0] and RSSI[2:0] are processed by the AD6620. This clock allows adequate setup and hold time for AB_OUT, D[10:0], and RSSI[2: captured by the AD6620 ...
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... AD6600 44-Terminal LQFP (Low-Profile Quad Plastic Flatpack) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). (ST-44) 0.063 (1.60) MAX 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN 0.006 (0.15) 0.002 (0.05) 0.018 (0.45) 0.031 (0.80) 0.057 (1.45) BSC 0.012 (0.30) 0.053 (1.35 0.394 (10. ...