MC9S12XDP512 Freescale Semiconductor, Inc, MC9S12XDP512 Datasheet
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MC9S12XDP512 Summary of contents
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... MC9S12XDP512 Data Sheet Covers S12XD, S12XB & S12XA Families HCS12X Microcontrollers MC9S12XDP512 Rev. 2.17 July 2007 freescale.com ...
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... MC9S12XDP512 Data Sheet MC9S12XDP512 Rev. 2.17 July 2007 ...
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... Updated App. E 6SCI’s on 112 pin DT/P512 and 3 SPI’s on all D256 parts Data Sheet covers S12XD/B & A Family 2.14 Included differnt pull device specification for differnt masksets 2.15 Minor Corrections and Improvments 2.16 Added 2M42E and 1M84E masksets 2.17 Modified Appendix MC9S12XDP512 Data Sheet, Rev. 2.17 Description Freescale Semiconductor ...
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... Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 5 ...
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... MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
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... Chapter 20 S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . 745 Chapter 21 External Bus Interface (S12XEBIV2 787 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2 807 Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2 901 Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2 975 Freescale Semiconductor Title MC9S12XDP512 Data Sheet, Rev. 2.17 Page 5 ...
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... Security (S12X9SECV2 1231 Appendix A Electrical Characteristics 1239 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290 Appendix C Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . 1294 Appendix D Using L15Y Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 Appendix E Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300 Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308 Appendix G Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309 6 Title MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... XFC — External Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.2.3 RESET — Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 2.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Freescale Semiconductor Title Chapter 2 — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . . 82 MC9S12XDP512 Data Sheet, Rev. 2.17 Page 9 ...
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... High Reference Voltage Pin, Low Reference Voltage Pin . . . . . . . . . . . . 127 RH RL 4.2 — Analog Circuitry Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . 127 DDA SSA 4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10 Title Chapter 3 — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 120 Chapter 4 Block Description MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 6.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.1 XGATE RISC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Freescale Semiconductor Title — Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.17 Page 11 ...
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... IOC0 — Input Capture and Output Compare Channel 311 7.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 7.4.1 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 7.4.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 12 Title Chapter 7 MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 9.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 9.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 9.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Freescale Semiconductor Title Chapter 8 Chapter 9 MC9S12XDP512 Data Sheet, Rev. 2.17 Page 13 ...
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... MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 10.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 Serial Communication Interface (S12SCIV5) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 11.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 14 Title Chapter 10 Chapter 11 MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 12.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 12.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 12.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 12.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 12.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 12.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Freescale Semiconductor Title Chapter 12 MC9S12XDP512 Data Sheet, Rev. 2.17 Page 15 ...
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... Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 14.4.2 Regulator Core (REG 564 14.4.3 Low-Voltage Detect (LVD 565 14.4.4 Power-On Reset (POR 565 14.4.5 Low-Voltage Reset (LVR 565 14.4.6 Regulator Control (CTRL 565 16 Title Chapter 13 Chapter 14 MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 16.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 16.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 16.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 16.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 Freescale Semiconductor Title Chapter 15 Chapter 16 Interrupt (S12XINTV1) MC9S12XDP512 Data Sheet, Rev. 2.17 Page 17 ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 18.1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 18.1.3 S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 18.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 18.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 18.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18 Title Chapter 17 Chapter 18 MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 20.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 20.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 20.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 20.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Freescale Semiconductor Title Chapter 19 Debug (S12XDBGV2) Chapter 20 MC9S12XDP512 Data Sheet, Rev. 2.17 Page 19 ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 22.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 22.2.1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 22.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 20 Title Chapter 21 Chapter 22 MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... Table 24-1.Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 24.0.4 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 24.0.5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 Table 24-59.Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 24.0.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 24.0.7 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 24.0.8 Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 24.0.9 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034 24.0.9.3Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 Freescale Semiconductor Title Chapter 23 Chapter 24 MC9S12XDP512 Data Sheet, Rev. 2.17 Page 21 ...
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... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 26.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 26.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 26.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086 26.4.1 EEPROM Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086 26.4.2 EEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 26.4.3 Illegal EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103 22 Title Chapter 25 Chapter 26 MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146 27.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1147 27.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.7.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.7.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148 Freescale Semiconductor Title Chapter 27 MC9S12XDP512 Data Sheet, Rev. 2.17 Page 23 ...
Page 24
... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 29.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 29.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 29.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 29.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 29.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 29.4.2 Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211 24 Title Chapter 28 Chapter 29 MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 A.2.1 ATD Operating Characteristics 1253 A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254 A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 Freescale Semiconductor Title Chapter 30 Security (S12X9SECV2) Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev. 2.17 Page 25 ...
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... E.4 MC9S12XD/A/B -Family SRAM & EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 1304 E.5 Peripheral Sets S12XD - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 E.6 Peripheral Sets S12XA & S12XB - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306 26 Title Appendix B Package Information Appendix C Recommended PCB Layout Appendix D Using L15Y Silicon Appendix E Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303 MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... Section Number E.7 Pinout explanations 1307 Freescale Semiconductor Title Appendix F Ordering Information Appendix G Detailed Register Map MC9S12XDP512 Data Sheet, Rev. 2.17 Page 27 ...
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... Section Number 28 Title MC9S12XDP512 Data Sheet, Rev. 2.17 Page Freescale Semiconductor ...
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... Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 1105 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 1147 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 1189 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 157 Freescale Semiconductor NOTE Table 0-1. Maskset Specific Documentation MC9S12XDP512 Data Sheet, Rev. 2.17 Table 0-1 shows the L15Y M84E M42E (512k ...
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... Chapter 1 Device Overview MC9S12XD-Family and register map of the cover part MC9S12XDP512 (maskset L15Y). For availability of the modules on other members of the S12XA, S12XB and S12XD families please refer to Differences. For pinout explanations of the different parts refer to available partnames /masksets refer to 30 describes pinouts, detailed pin description , interrupts Table 1-6 ...
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... Family members in 144-pin LQFP will be available with external bus interface and parts in 112-pin LQFP or 80-pin QFP package without external bus interface. See optioÔÛÆ@» Freescale Semiconductor Appendix E Derivative Differences MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family for package 31 ...
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... Chapter 1 Device Overview MC9S12XD-Family 1.1.1 MC9S12XD/B/A Family Features This section lists the features which are available on MC9S12XDP512. See Appendix E Derivative Differences sizes on other family members. • HCS12X Core — 16-bit HCS12X CPU – Upward compatible with MC9S12 instruction set – Interrupt stacking and programmer’s model identical to MC9S12 – ...
Page 33
... LQFP, 112-pin LQFP, and 80-pin QFP packages — I/O lines with 5-V input and drive capability — Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation — 5-V A/D converter inputs — Operation at 80 MHz equivalent to 40-MHz bus speed Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family 33 ...
Page 34
... System wait mode 1.1.3 Block Diagram Figure 1-1 shows a block diagram of theMC9S12X-Family. The block diagram shows all modules available on cover part MC9S12XDP512. Availability of modules on other family members see Appendix E Derivative Differences. ATD Converter is routed to pins PAD00 - PAD15 on maskset M42E. See Converter (ATD10B16CV4) Block Description ...
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... VSSA PWM I/O Supply 3 DDX1,2 V SSX1,2 Voltage Regulator 3 DDR1,2 SPI1 V SSR1,2 RXD SCI4 TXD SPI2 RXD SCI5 TXD Figure 1-1. MC9S12XD-Family Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family ATD1 DDA DDA ...
Page 36
... DDPLL IIC0 V SSPLL Analog Supply 3-5 V VDDA VSSA PWM I/O Supply 3 DDX V SSX Voltage Regulator 3 DDR SPI1 V SSR Figure 1-2. Block Diagram Maskset M42E MC9S12XDP512 Data Sheet, Rev. 2. ATD1 V V DDA V V SSA AN0 PAD00 AN1 PAD01 AN2 PAD02 ...
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... Device Memory Map Table 1-1shows the device register memory map of the MC9S12XDP512. Available modules on other Family members please refer to Unimplemented register space shown in locations have no effect. Read access to these locations returns zero. mapping for the parts listed in Address 0x0000–0x0009 0x000A–0x000B 0x000C– ...
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... PIM (port integration module) CAN4 (scalable CAN) Reserved ATD0 (analog-to-digital converter 10 bit 8-channel) Unimplemented Voltage regulator Unimplemented PWM (pulse-width modulator 8 channels) Unimplemented Periodic interrupt timer Unimplemented XGATE Unimplemented Unimplemented MC9S12XDP512 Data Sheet, Rev. 2.17 Size (Bytes 192 64 64 ...
Page 39
... Figure 1-3. S12X CPU & BDM Global Address Mapping Freescale Semiconductor 0x00_0000 0x00_07FF RAM_LOW 0x0F_FFFF EPAGE RPAGE EEPROM_LOW 0x13_FFFF 0x1F_FFFF PPAGE 0x3F_FFFF FLASH_LOW 0x7F_FFFF MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family Global Memory Map 2K REGISTERS Unimplemented RAM RAM Unimplemented EEPROM EEPROM External Space Unimplemented FLASH FLASH ...
Page 40
... MC9S12XDP512 Data Sheet, Rev. 2.17 Figure 1-3) FLASHSIZE/ FLASH_LOW 512K 0x78_0000 512K 0x78_0000 512K 0x78_0000 128K 7E_0000 128K 7E_0000 128K 7E_0000 64K 7F_0000 128K 7E_0000 128K ...
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... Freescale Semiconductor 0x00_0000 0x00_07FF RAM_LOW 0x0F_FFFF EPAGE RPAGE EEPROM_LOW 0x13_FFFF 0x1F_FFFF PPAGE 0x3F_FFFF 0x78_0000 FLASH0_LOW FLASH1_HIGH 0x7F_FFFF MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family Global Memory Map 2K REGISTERS Unimplemented RAM RAM Unimplemented EEPROM EEPROM External Space Unimplemented FLASH FLASH0 Unimplemented ...
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... EEPROMSIZE/ FLASHSIZE0/ EEPROM_LOW FLASH_LOW 4K 0x13_F000 0x79_FFFF 4K 0x13_F000 4K 0x13_F000 4K 0x13_F000 0x79_FFFF 4K 0x13_F000 2K 0x13_F800 MC9S12XDP512 Data Sheet, Rev. 2.17 Figure 1-4) FLASHSIZE1/ FLASH_HIGH 128K 256K 0x7C_0000 128K 128K 0x7E_0000 Freescale Semiconductor ...
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... XGATE Local Memory Map 0x0000 Registers 0x0800 FLASH RAM 0xFFFF Freescale Semiconductor Figure 1-5. GATE Global Address Mapping XGRAM_LOW XGFLASH_HIGH MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family Global Memory Map 0x00_0000 Registers 0x00_07FF RAM 0x0F_FFFF 0x78_0800 FLASH 0x7F_FFFF 43 ...
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... Available Flah Memory 30K on all listed parts 44 Table 1-4. XGATE Resources (see XGRANMSIZE XGRAM_LOW 32K 0x0F_8000 20K 0x0F_B000 20K 0x0F_B000 32K 0x0F_8000 16K 0x0F_C000 16K 0x0F_C000 10K 0x0F_D800 16K 0x0F_C000 MC9S12XDP512 Data Sheet, Rev. 2.17 Figure 1-5) 1 XGFLASHSIZE XGFLASH_HIGH 30K 0x78_7FFF Freescale Semiconductor ...
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... XGATE Local Memory Map 0x0000 Registers 0x0800 RAM 0xFFFF Freescale Semiconductor Figure 1-6. XGATE Global Address Mapping MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family Global Memory Map 0x00_0000 Registers 0x00_07FF XGRAM_LOW RAM 0x0F_FFFF 0x7F_FFFF 45 ...
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... Chapter 1 Device Overview MC9S12XD-Family Device 9S12XDG128 3S12XDG128 9S12XD128 9S12XD64 9S12XB128 9S12XA128 46 Table 1-5. XGATE Resources (see XGRAMSIZE 12K 12K 12K MC9S12XDP512 Data Sheet, Rev. 2.17 Figure 1-6) XGRAM_LOW 0x0F_D000 0x0F_D000 0x0F_E000 0x0F_F000 0x0F_E800 0x0F_D000 Freescale Semiconductor ...
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... MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family Table 1-6 shows the assigned part ID 1 Part ID 0xC410/0xC411 0xC410/0xC411 0xC410/0xC411 0xC410/0xC411 0xC410/0xC411 0xC000/0xC001 0xC410/0xC411 0xC000/0xC001 0xC410/0xC411 0xC000/0xC001 ...
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... Not all functions are shown in the following pinouts. Please refer to Table 1-7 on different family members refer to For pinout explanations of the different parts refer to explanations: 48 for package options. CAUTION for a complete description. For avalability of the modules Appendix E Derivative MC9S12XDP512 Data Sheet, Rev. 2.17 Differences. E.7 Pinout Freescale Semiconductor ...
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... MC9S12XD-Family 144-Pin LQFP Pins shown in BOLD-ITALICS are not available on the 112-Pin LQFP or the 80-Pin QFP package option Pins shown in BOLD are not available on the 80-Pin QFP package option MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family 108 VRH 107 VDDA 106 ...
Page 50
... MODC/BKGD 23 PB0 24 PB1 25 PB2 26 PB3 27 PB4 28 Figure 1-8. MC9S12XD Family Pin Assignments 112-Pin LQFP Package 50 MC9S12XD-Family 112-Pin LQFP Pins shown in BOLD are not available on the 80-Pin QFP package option MC9S12XDP512 Data Sheet, Rev. 2.17 84 VRH 83 VDDA 82 PAD15/AN15 81 PAD07/AN07 80 PAD14/AN14 79 PAD06/AN06 78 PAD13/AN13 77 PAD05/AN05 76 PAD12/AN12 ...
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... Figure 1-9. MC9S12XD Family Pin Assignments 80-Pin QFP Package Freescale Semiconductor MC9S12XD-Family 11 80-Pin QFP MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family 60 VRH 59 VDDA 58 PAD07/AN07 57 PAD06/AN06 56 PAD05/AN05 55 PAD04/AN04 54 PAD03/AN03 53 PAD02/AN02 52 PAD01/AN01 51 PAD00/AN00 50 VSS2 ...
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... Chapter 1 Device Overview MC9S12XD-Family 1.2.2 Signal Properties Summary Table 1-7 summarizes the pin functionality of the MC9S12XDP512. For available modules on other parts of the S12XD, S12XB and S12XA family please refer to Table 1-7. Signal Properties Summary (Sheet Pin Pin Pin Name Name Name Function 1 Function 2 ...
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... V DDX — — V DDX — — V DDX — — V DDX MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family Internal Pull Resistor Description Reset CTRL State PUCR Up Port E input, non-maskable interrupt SPI2, TXD of SCI5 PERH/ Disabled Port H I/O, interrupt, SCK of PPSH ...
Page 54
... V DDX MOSI1 — V DDX MISO1 — V DDX — — V DDX — — V DDX MC9S12XDP512 Data Sheet, Rev. 2.17 Internal Pull Resistor Description Reset CTRL State PUCR Up Extended address, PIPE status PUCR Up Extended address, PIPE status PUCR Up Extended address, PIPE status PERM/ ...
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... Refer to 1.2.3 Detailed Signal Descriptions This section describes all pins which are availabe on the cover part MC9S12XDP512 in 144-pin LQFP package. For modules and pinout explanations of the different family members refer to explanations: and Sets S12XA & S12XB - Family 1.2.3.1 EXTAL, XTAL — ...
Page 56
... PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD1 PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital converter ATD1. 56 NOTE in all applications DDPLL C S MCU R 0 XFC Figure 1-10. PLL Loop Filter Connections MC9S12XDP512 Data Sheet, Rev. 2.17 V DDPLL C P Freescale Semiconductor ...
Page 57
... PE7 is a general-purpose input or output pin. The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family 57 ...
Page 58
... The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a 58 EXTAL C 1 MCU Crystal or Ceramic Resonator XTAL Ceramic Resonator R S CMOS-Compatible EXTAL External Oscillator MCU XTAL Not Connected MC9S12XDP512 Data Sheet, Rev. 2.17 V SSPLL C 1 Crystal SSPLL Freescale Semiconductor ...
Page 59
... PE0 / XIRQ — Port E Input Pin 0 PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family 59 ...
Page 60
... PH1 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 1 (SPI1). 60 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
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... PJ0 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as the receive pin RXD of the serial communication interface 2 (SCI2).It can be configured to provide a chip-select output. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family 61 ...
Page 62
... PM5 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controllers (CAN0, CAN2, or CAN4). It can be configured as the serial clock pin SCK of the serial peripheral interface 0 (SPI0). 62 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 63
... PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5 PP5 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 5 output. It can Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family 63 ...
Page 64
... PS7 is a general-purpose input or output pin. It can be configured as the slave select pin SS of the serial peripheral interface 0 (SPI0). 1.2.3.61 PS6 / SCK0 — Port S I/O Pin 6 PS6 is a general-purpose input or output pin. It can be configured as the serial clock pin SCK of the serial peripheral interface 0 (SPI0). 64 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
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... PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] PT[7:0] are general-purpose input or output pins. They can be configured as input capture or output compare pins IOC[7:0] of the enhanced capture timer (ECT). 1.2.4 Power Supply Pins MC9S12XDP512 power and ground pins are described below. All V pins must be connected together in the application. SS 1.2.4.1 ...
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... No load allowed except for bypass capacitors — Power and Ground Pins for I/O Drivers SSR1 SSR2 , V — Core Power Pins SS1 SS2 and V . Because fast signal transitions place high NOTE — Power Supply Pins for PLL NOTE MC9S12XDP512 Data Sheet, Rev. 2.17 REG Freescale Semiconductor ...
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... 2 MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family Description Internal power and ground generated by internal regulator External power and ground, supply to pin drivers and internal voltage regulator External power and ground, supply to pin drivers External power and ground, supply to pin ...
Page 68
... CRG to all modules. CAN Modules Oscillator Clock Core Clock S12X XGATE 1-12, this system clocks are used throughout the MCU to drive the core, the MC9S12XDP512 Data Sheet, Rev. 2.17 IIC Modules ATD Modules PIT ECT PIM FLASH ...
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... MODC signal during reset. The MODC bit in the MODE register shows the current operating mode and provide limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge of RESET. Freescale Semiconductor CAUTION MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family Appendix E Table 1-9.) For ...
Page 70
... Loop controlled Pierce oscillator selected determines whether the on-chip voltage REGEN Table 1-11). Table 1-11. Voltage Regulator VREGEN Description Internal voltage regulator enabled Internal voltage regulator disabled, V supplied externally MC9S12XDP512 Data Sheet, Rev. 2.17 PK7 = PE3 = Data Source EROMCTL X X Internal X 0 Emulation memory ...
Page 71
... The microcontroller features two main low-power modes. Consult the respective sections for information on the module behavior in system stop, system pseudo stop, and system wait mode. An important source of information about the clock system is the Clock and Reset Generator S12CRG section. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family 71 ...
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... Associated with each I-bit maskable service request is a configuration register. It selects if the service request is enabled, the service request priority level and whether the service request is handled either by the S12X CPU or by the XGATE module. 72 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
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... Reserved ATD1 Port J Port H Modulus down counter underflow Pulse accumulator B overflow CRG PLL lock CRG self-clock mode Reserved IIC0 bus MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family CCR Local Enable Mask None None None PLLCTL (CME, SCME) None ...
Page 74
... CAN3 receive CAN3 transmit Reserved Reserved CAN4 wake-up CAN4 errors CAN4 receive CAN4 transmit Port P Interrupt PWM emergency shutdown SCI2 MC9S12XDP512 Data Sheet, Rev. 2.17 CCR Local Enable Mask I bit SPI1CR1 (SPIE, SPTIE) I bit SPI2CR1 (SPIE, SPTIE) I bit ECNFG (CCIE, CBEIE) I bit ...
Page 75
... XGATE software trigger 4 XGATE software trigger 5 XGATE software trigger 6 XGATE software trigger 7 XGATE software error interrupt S12XCPU RAM access violation Reserved Spurious interrupt MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 1 Device Overview MC9S12XD-Family CCR Local Enable Mask I bit SCI3CR2 (TIE, TCIE, RIE, ILIE) ...
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... Table 1-13. Initial COP Rate Configuration NV[2:0] in CR[2:0] in COPCTL Register 000 001 010 011 100 101 110 111 Table 1-14. Initial WCOP Configuration NV[3] in COPCTL Register 1 0 MC9S12XDP512 Data Sheet, Rev. 2.17 111 110 101 100 011 010 001 000 WCOP Freescale Semiconductor ...
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... ATD0 External Trigger Input Connection The ATD_10B8C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG, and ETRIG3. The external trigger allows the user to synchronize ATD conversion to external trigger events. shows the connection of the external trigger inputs on MC9S12XDP512. External Trigger Input ...
Page 78
... Chapter 1 Device Overview MC9S12XD-Family 78 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 79
... System reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 79 ...
Page 80
... Self clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 80 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
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... OSCCLK Checker COP Registers PLLCLK Clock and Reset PLL Control Figure 2-1. CRG Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 2 Clocks and Reset Generator (S12CRGV6) System Reset Bus Clock Core Clock RTI Oscillator Clock Real Time Interrupt PLL Lock Interrupt Self Clock Mode ...
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... This section provides a detailed description of all registers accessible in the CRG. 82 — Operating and Ground Voltage Pins SSPLL ) and ground (V DDPLL C S MCU R S XFC Figure 2-2. PLL Loop Filter Connections MC9S12XDP512 Data Sheet, Rev. 2.17 ) for the PLL circuitry. This allows SSPLL V DDPLL C P Freescale Semiconductor DDPLL ...
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... CRG Clock Select Register (CLKSEL) CRG PLL Control Register (PLLCTL) CRG RTI Control Register (RTICTL) CRG COP Control Register (COPCTL) CRG Test Control Register (CTCTL) CRG COP Arm/Timer Reset (ARMCOP) NOTE MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 2 Clocks and Reset Generator (S12CRGV6) Access R/W R/W 1 R/W ...
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... PSTP PLLON AUTO ACQ RTR6 RTR5 RTR4 0 0 WRTMASK Bit 6 Bit 5 Bit 4 Figure 2-3. S12CRGV6 Register Summary MC9S12XDP512 Data Sheet, Rev. 2. SYN3 SYN2 SYN1 REFDV3 REFDV2 REFDV1 LOCK TRACK SCMIF 0 0 SCMIE 0 PLLWAI RTIWAI FSTWKP PRE ...
Page 85
... REFDV + 1 NOTE 5 4 SYN5 SYN4 0 0 Figure 2-4. CRG Synthesizer Register (SYNR) NOTE 5 4 REFDV5 REFDV4 REFDV3 0 0 NOTE MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 2 Clocks and Reset Generator (S12CRGV6) ). SCM SYN3 SYN2 SYN1 REFDV2 REFDV1 SYN0 ...
Page 86
... Power on reset has occurred Figure 2-6. Reserved Register (CTFLG) NOTE 5 4 LOCK LVRF LOCKIF 2 0 Figure 2-7. CRG Flags Register (CRGFLG) Table 2-2. CRGFLG Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. TRACK SCMIF Freescale Semiconductor 0 ...
Page 87
... SCM 0 MCU is operating normally with OSCCLK available. 1 MCU is operating in self clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency f Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Description . SCM MC9S12XDP512 Data Sheet, Rev. 2.17 87 ...
Page 88
... Interrupt will be requested whenever LOCKIF is set. 1 Self ClockMmode Interrupt Enable Bit SCMIE 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set LOCKIE Table 2-3. CRGINT Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. SCMIE Freescale Semiconductor ...
Page 89
... COP stops and initializes the COP counter whenever the part goes into wait mode. Freescale Semiconductor Figure 2- PLLWAI Table 2-4. CLKSEL Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 2 Clocks and Reset Generator (S12CRGV6) for more details on the effect of each bit RTIWAI COPWAI 0 89 ...
Page 90
... CRG will switch all system clocks to OSCCLK. The SCMIF flag will be set. See application examples in Figure 2-23 and Figure AUTO ACQ FSTWKP Table 2-5. PLLCTL Field Descriptions Description Checker”). The SCMIF flag will not be set. The system will remain in self-clock 2-24. MC9S12XDP512 Data Sheet, Rev. 2. PRE PCE SCME Freescale Semiconductor ...
Page 91
... RTR5 RTR4 RTR3 NOTE Table 2-6. RTICTL Field Descriptions Description Table 2-7 Table 2-8 and Table 2-8 show all possible divide values selectable by the RTICTL MC9S12XDP512 Data Sheet, Rev. 2.17 Section 2.5.2, “Clock Monitor Reset”). Section 2.4.2.2, “Self Clock Mode”). RTR2 RTR1 RTR0 ...
Page 92
... MC9S12XDP512 Data Sheet, Rev. 2.17 100 101 110 2x2 2x2 2x2 3x2 3x2 3x2 13 ...
Page 93
... MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 2 Clocks and Reset Generator (S12CRGV6) 101 110 (50x10 ) (100x10 ) 50x10 100x10 100x10 200x10 150x10 ...
Page 94
... Allows the COP and RTI to keep running in active BDM mode. 1 Stops the COP and RTI counters whenever the part is in active BDM mode WRTMASK Table 2-9. COPCTL Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. CR2 CR1 CR0 Table 2-10 shows the duration Freescale Semiconductor ...
Page 95
... COP mode (Window COP mode disabled): Table 2-10. COP Watchdog Rates CR1 CR0 Cycles to Time-out MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-10). The COP 1 OSCCLK COP disabled ...
Page 96
... Read: always read 0x_80 except in special modes Write: only in special modes 96 NOTE Figure 2-13. Reserved Register (FORBYP) NOTE Figure 2-14. Reserved Register (CTCTL) MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...
Page 97
... COP reset. Freescale Semiconductor Bit 5 Bit 4 Bit Figure 2-15. ARMCOP Register Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 2 Clocks and Reset Generator (S12CRGV6 Bit 2 Bit Bit ...
Page 98
... SYNR PLLCLK = 2 OSCCLK ----------------------------------- - REFDV CAUTION REFERENCE REFDV <5:0> FEEDBACK REFERENCE PROGRAMMABLE DIVIDER LOOP PROGRAMMABLE DIVIDER SYN <5:0> Figure 2-16. PLL Functional Diagram MC9S12XDP512 Data Sheet, Rev. 2. LOCK LOCK DETECTOR V /V DDPLL SSPLL UP PDET PHASE CPUMP VCO DOWN DETECTOR V DDPLL LOOP FILTER ...
Page 99
... LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev. 2.17 Figure 2-16. . This is the self clock mode DDPLL ...
Page 100
... STOP 1 SYSCLK 0 SCM WAIT(RTIWAI), STOP(PSTP,PRE), RTI ENABLE 1 0 WAIT(COPWAI), STOP(PSTP,PCE), COP ENABLE STOP Figure 2-17. System Clocks Generator MC9S12XDP512 Data Sheet, Rev. 2.17 , and is clear when trk , and is cleared Lock . ) before acq ) before selecting the PLLCLK al CORE CLOCK 2 CLOCK PHASE BUS CLOCK GENERATOR ...
Page 101
... VCO clock cycles are generated by the PLL when running at minimum frequency f Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Figure Figure 2-18. But note that a CPU cycle corresponds called check window. MC9S12XDP512 Data Sheet, Rev. 2.17 2-17). The gating condition placed on Section 2.4.2.2, “Self Clock . The bus SCM . SCM 101 ...
Page 102
... Figure 2-19. Check Window Example Figure 2-20. CM fail yes num = 0 Enter SCM Clock Monitor Reset Enter SCM num=num–1 yes no num > Switch to OSCCLK Exit SCM MC9S12XDP512 Data Sheet, Rev. 2.17 Figure 2- example. 49999 50000 no FSTWKP = 0 ? yes num = 0 no yes SCM active? yes no ...
Page 103
... The CRG block behaves as described within this specification in all normal modes Clock Monitor Reset will always set the SCME bit to logical 1. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) NOTE 1 handling the clock quality checker continues to SCM Section 2.4.1.5, “Computer Operating Properly MC9S12XDP512 Data Sheet, Rev. 2.17 ) and an active VREG 103 ...
Page 104
... If the external clock frequency is not available due SCM NOTE PLLWAI RTIWAI Stopped — RTI — Stopped — — (Figure 2-21). Depending on the configuration, the CRG MC9S12XDP512 Data Sheet, Rev. 2.17 Section 2.4.1.4, “Clock Quality COPWAI — — Stopped Freescale Semiconductor ...
Page 105
... Wait Mode left Exit Wait w. ext.RESET No Exit Wait w. CMRESET SCMIE=1 Generate SCM Interrupt (Wakeup from Wait) Wait Mode Continue w. Normal OP Figure 2-21. Wait Mode Entry/Exit Sequence MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 2 Clocks and Reset Generator (S12CRGV6 CME=1 INT ? ? Yes Yes No CM Fail ? Yes ...
Page 106
... A complete timeout window check will be started when stop mode is left again. Wake-up from stop mode also depends on the setting of the PSTP bit. 106 MC9S12XDP512 Data Sheet, Rev. 2.17 (Section 2.4.1.4, “Clock Freescale Semiconductor ...
Page 107
... Start clock quality check, – SCMIF set. – Exit wait mode in SCM using PLL clock (f – Continue to perform a additional clock quality checks until OSCCLK is o.k. again. MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 2 Clocks and Reset Generator (S12CRGV6 system clock, SCM ) as system clock, ...
Page 108
... OK CMRESET ? Yes Exit Stop Mode Generate SCM Interrupt (Wakeup from Stop) Exit Stop Mode Enter SCM SCMIF not set! Continue w. normal OP Figure 2-22. Stop Mode Entry/Exit Sequence MC9S12XDP512 Data Sheet, Rev. 2.17 Yes No CME=1 INT ? ? Yes Yes No CM fail ? Yes no SCME=1 ? Yes Exit ...
Page 109
... PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 2-13 summarizes the outcome of a clock loss while in pseudo stop mode. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev. 2.17 (Section 2.4.1.4, “Clock 109 ...
Page 110
... Start clock quality check, – SCMIF set. SCMIF generates self clock mode wakeup interrupt. – Exit pseudo stop mode in SCM using PLL clock (f – Continue to perform a additional clock quality checks until OSCCLK is o.k. again. MC9S12XDP512 Data Sheet, Rev. 2.17 CRG Actions ) as system clock SCM ) as system clock ...
Page 111
... In full stop mode or self-clock mode caused by the fast wake-up feature, the clock monitor and the oscillator are disabled. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Checker”). After completing the clock quality check NOTE MC9S12XDP512 Data Sheet, Rev. 2.17 Section 2.4.1.4, Section 2.4.1.4, “Clock Figure 2-23 and Figure 2-24 ...
Page 112
... STOP Interrupt Interrupt Power Saving Oscillator Disabled Self-Clock Mode IRQ Service FSTWKP=0 SCMIE=1 OSC Startup Self-Clock Mode MC9S12XDP512 Data Sheet, Rev. 2.17 IRQ Service IRQ Service STOP Interrupt Freq. Critical Freq. Uncritical Instructions Instr. Possible SCM Interrupt Clock Quality Check Freescale Semiconductor ...
Page 113
... Chapter 2 Clocks and Reset Generator (S12CRGV6) Section 2.3, “Memory Map and Register Table 2-14. Refer to MCU specification for related vector Table 2-14. Reset Summary Local Enable PLLCTL (CME = 1, SCME = 0) COPCTL (CR[2:0] nonzero) Table 2-15 shows which vector will be fetched. MC9S12XDP512 Data Sheet, Rev. 2.17 None None None None 113 ...
Page 114
... With n being Possibly min 3 / max 6 SYSCLK cycles depending not on internal running synchronization delay Figure 2-25. RESET Timing MC9S12XDP512 Data Sheet, Rev. 2.17 Vector Fetch Clock Monitor Reset COP Reset with rise of RESET pin ) ) ( ( 64 cycles Possibly RESET driven low externally Freescale Semiconductor ...
Page 115
... RESET pin is tied to V and when the RESET pin is held low. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) to the MCU has reached a certain level and asserts power DD MC9S12XDP512 Data Sheet, Rev. 2.17 Section 2.3, DD 115 ...
Page 116
... Self Clock Mode 128 SYSCLK 64 SYSCLK ) ( Figure 2-27. RESET Pin Held Low Externally Table 2-16. CRG Interrupt Vectors CCR Mask I bit I bit CRGINT (LOCKIE) I bit CRGINT (SCMIE) MC9S12XDP512 Data Sheet, Rev. 2.17 Table 2-16. Refer to MCU specification for Local Enable CRGINT (RTIE) Freescale Semiconductor ...
Page 117
... SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set to1 when the SCM condition has changed, and is cleared writing the SCMIF bit. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Section 2.4.1.4, “Clock Quality MC9S12XDP512 Data Sheet, Rev. 2.17 Checker”. If the clock monitor is 117 ...
Page 118
... Chapter 2 Clocks and Reset Generator (S12CRGV6) 118 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 119
... Clock monitor 3.1.2 Modes of Operation Two modes of operation exist: 1. Loop controlled Pierce oscillator 2. External square wave mode featuring also full swing Pierce without internal feedback resistor Freescale Semiconductor supply rail (2.5 V nominal) and require the minimum number DDPLL MC9S12XDP512 Data Sheet, Rev. 2.17 119 ...
Page 120
... XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived from the 120 Monitor_Failure Clock Monitor Gain Control V DDPLL Rf Figure 3-1. XOSC Block Diagram — Operating and Ground Voltage Pins SSPLL ) and ground (V DDPLL MC9S12XDP512 Data Sheet, Rev. 2.17 OSCCLK = 2.5 V XTAL ) for the XOSC circuitry. This SSPLL Freescale Semiconductor ...
Page 121
... Figure 3-4. External Clock Connections (XCLKS = 0) Freescale Semiconductor NOTE EXTAL C1 MCU Crystal or Ceramic Resonator XTAL C2 NOTE RB Crystal or Ceramic Resonator RS* CMOS Compatible EXTAL External Oscillator (V DDPLL MCU XTAL Not Connected MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 3 Pierce Oscillator (S12XOSCLCPV1) V SSPLL SSPLL Level) 121 ...
Page 122
... CME control bit, described in the CRG block description chapter. 122 Table 3-1. Clock Selection Based on XCLKS Description Loop controlled Pierce oscillator selected Full swing Pierce oscillator/external clock selected power supply pins. SSPLL MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 123
... During wait mode, XOSC is not impacted. 3.4.4 Stop Mode Operation XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 123 ...
Page 124
... Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 124 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 125
... Configurable location for channel wrap around (when converting multiple channels in a sequence) 4.1.2 Modes of Operation There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 4.1.3 Block Diagram Refer to Figure 4-1 for a block diagram of the ATD0B16C block. Freescale Semiconductor chapter for ATD accuracy. MC9S12XDP512 Data Sheet, Rev. 2.17 125 ...
Page 126
... Mode and Mux Timing Control ATDDIEN PORTAD Successive Approximation Register (SAR) and DAC Sample & Hold 1 Analog MUX Figure 4-1. ATD10B16C Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 ATD10B16C Sequence Complete Interrupt Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 ATD 8 ATD 9 ...
Page 127
... This section provides a detailed description of all registers accessible in the ATD10B16C. 4.3.1 Module Memory Map Table 4-1 gives an overview of all ATD10B16C registers Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description chapter for availability and connectivity of these inputs. is the low reference voltage for ATD conversion. RL MC9S12XDP512 Data Sheet, Rev. 2.17 127 ...
Page 128
... ATD Result Register 9 (ATDDR9H, ATDDR9L) ATD Result Register 10 (ATDDR10H, ATDDR10L) ATD Result Register 11 (ATDDR11H, ATDDR11L) ATD Result Register 12 (ATDDR12H, ATDDR12L) ATD Result Register 13 (ATDDR13H, ATDDR13L) ATD Result Register 14 (ATDDR14H, ATDDR14L) ATD Result Register 15 (ATDDR15H, ATDDR15L) NOTE MC9S12XDP512 Data Sheet, Rev. 2.17 Access R/W R/W R/W R/W R/W R/W ...
Page 129
... MULT 0 ETORF FIFOR Unimplemented Unimplemented CCF14 CCF13 CCF12 CCF6 CCF5 CCF4 IEN14 IEN13 IEN12 = Unimplemented or Reserved Figure 4-2. ATD Register Summary MC9S12XDP512 Data Sheet, Rev. 2. WRAP3 WRAP2 WRAP1 ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 ETRIGP ETRIGE ASCIE S1C FIFO FRZ1 PRS3 PRS2 PRS1 ...
Page 130
... BIT 6 BIT 6 BIT 5 BIT 4 BIT Unimplemented or Reserved WRAP3 0 0 Table 4-2. ATDCTL0 Field Descriptions Description Table MC9S12XDP512 Data Sheet, Rev. 2. IEN3 IEN2 IEN1 PTAD11 PTAD10 PTAD9 PTAD3 PTAD2 PTAD1 BIT 5 BIT 4 BIT 3 BIT 3 BIT 2 BIT ...
Page 131
... ETRIGCH3 0 0 Table 4-4. ATDCTL1 Field Descriptions Description Table 4-5. MC9S12XDP512 Data Sheet, Rev. 2.17 after Converting Reserved AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ETRIGCH2 ETRIGCH1 ...
Page 132
... MC9S12XDP512 Data Sheet, Rev. 2.17 External Trigger Source AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 1 ETRIG0 1 ETRIG1 1 ETRIG2 1 ETRIG3 Reserved ...
Page 133
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description AWAI ETRIGLE ETRIGP Table 4-6. ATDCTL2 Field Descriptions Description Table 4-5. If external trigger source is one of the AD channels, the digital (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect. MC9S12XDP512 Data Sheet, Rev. 2. ASCIF ETRIGE ASCIE Table 4-7 for 133 ...
Page 134
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description ETRIGLE 134 Table 4-7. External Trigger Configurations ETRIGP External Trigger Sensitivity 0 Falling Edge 1 Ring Edge 0 Low Level 1 High Level MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 135
... At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description S4C S2C S1C Table 4-8. ATDCTL3 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. FIFO FRZ1 FRZ0 Table 4-9 shows Table 4-9 shows Table 4-9 ...
Page 136
... S1C per Sequence MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...
Page 137
... Table 4-10. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description FRZ0 Behavior in Freeze Mode 0 Continue conversion 1 Reserved 0 Finish current conversion, then freeze 1 Freeze Immediately MC9S12XDP512 Data Sheet, Rev. 2.17 137 ...
Page 138
... BusClock = ------------------------------- - 0.5 PRS + 1 Table 4-12. Sample Time Select SMP0 Length of 2nd Phase of Sample Time 0 2 A/D conversion clock periods 1 4 A/D conversion clock periods 0 8 A/D conversion clock periods 1 16 A/D conversion clock periods MC9S12XDP512 Data Sheet, Rev. 2. PRS2 PRS1 Freescale Semiconductor 0 PRS0 1 ...
Page 139
... Divide by 54 108 MHz Divide by 56 112 MHz Divide by 58 116 MHz Divide by 60 120 MHz Divide by 62 124 MHz Divide by 64 128 MHz MC9S12XDP512 Data Sheet, Rev. 2. Min. Bus Clock 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz ...
Page 140
... AN0 (channel 0. 0 Sample only one channel 1 Sample across several channels 140 SCAN MULT Table 4-14. ATDCTL5 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. for details. Freescale Semiconductor ...
Page 141
... Signed Unsigned 8-Bit Codes 8-Bit Codes MC9S12XDP512 Data Sheet, Rev. 2.17 Result Data Formats Signed Unsigned 10-Bit Codes 10-Bit Codes 7FC0 FFC0 7F00 FF00 7E00 FE00 0100 8100 0000 8000 FF00 7F00 8100 0100 ...
Page 142
... MC9S12XDP512 Data Sheet, Rev. 2.17 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Freescale Semiconductor ...
Page 143
... No External trigger over run error has occurred 1 External trigger over run error has occurred Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description CC3 ETORF FIFOR Table 4-18. ATDSTAT0 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. CC2 CC1 CC0 143 ...
Page 144
... If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. 144 Description MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 145
... Figure 4-10. Reserved Register 0 (ATDTEST0) NOTE Figure 4-11. Reserved Register 1 (ATDTEST1) NOTE Table 4-19. ATDTEST1 Field Descriptions Description Table 4-20 lists the coding. MC9S12XDP512 Data Sheet, Rev. 2. Unaffected Unaffected ...
Page 146
... Table 4-20. Special Channel Select Coding CCF13 CCF12 CCF11 0 0 Table 4-21. ATDSTAT2 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2.17 CA Analog Input Channel X Reserved Reserved X Reserved CCF10 ...
Page 147
... will be overwritten by the set. Conversion number x not completed Conversion number x has completed, result ready in ATDDRx Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description CCF5 CCF4 CCF3 Table 4-22. ATDSTAT1 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. CCF2 CCF1 CCF0 147 ...
Page 148
... IEN13 IEN12 IEN11 Table 4-23. ATDDIEN0 Field Descriptions Description IEN5 IEN4 IEN3 Table 4-24. ATDDIEN1 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. IEN10 IEN9 IEN8 IEN2 IEN1 IEN0 Freescale Semiconductor ...
Page 149
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 5 4 PTAD13 PTAD12 PTAD11 1 1 AN13 AN12 AN11 Figure 4-16. Port Data Register 0 (PORTAD0) Table 4-25. PORTAD0 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. PTAD10 PTAD9 AN10 AN9 specifications will have an indeterminate value)). IH 0 PTAD8 1 ...
Page 150
... Reset sets all PORTAD1 bits to “1”. 150 5 4 PTAD5 PTAD4 PTAD3 1 1 AN5 AN4 Figure 4-17. Port Data Register 1 (PORTAD1) Table 4-26. PORTAD1 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. PTAD2 PTAD1 AN3 AN2 AN1 specifications will have an indeterminate value)). IH Freescale Semiconductor 0 ...
Page 151
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description BIT 7 BIT 6 BIT 5 BIT 5 BIT 4 BIT MC9S12XDP512 Data Sheet, Rev. 2. BIT 4 BIT 3 BIT 2 BIT 2 BIT 1 BIT Unaffected ...
Page 152
... The input analog signals are unipolar and must fall within the potential range of V 152 BIT 5 BIT 4 BIT 3 BIT 5 BIT 4 BIT allow to isolate noise of other MCU circuitry from the analog sub-block. MC9S12XDP512 Data Sheet, Rev. 2. BIT 9 MSB BIT 2 BIT 1 BIT 2 BIT 1 0 ...
Page 153
... Falling edge triggered. Performs one conversion sequence per trigger. X Rising edge triggered. Performs one conversion sequence per trigger. X Trigger active low. Performs continuous conversions while trigger is active. X Trigger active high. Performs continuous conversions while trigger is active. MC9S12XDP512 Data Sheet, Rev. 2.17 (A/D reference potentials) will result RH Description 153 ...
Page 154
... In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. The reset value for the ADPU bit is zero. Therefore, when this module is reset reset into the power down state. 154 NOTE MC9S12XDP512 Data Sheet, Rev. 2.17 before initiating a new ATD SR Freescale Semiconductor ...
Page 155
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description which details the registers and their bit fields. Table 4-28. Refer to MCU specification for related Table 4-28. ATD Interrupt Vectors CCR Mask I bit for further details. MC9S12XDP512 Data Sheet, Rev. 2.17 Local Enable ASCIE in ATDCTL2 155 ...
Page 156
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 156 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 157
... Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XDP512 Data Sheet, Rev. 2.17 157 ...
Page 158
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 158 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 159
... Configurable location for channel wrap around (when converting multiple channels in a sequence). 5.1.2 Modes of Operation 5.1.2.1 Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.17 159 ...
Page 160
... V RH 5.2.4 V and V DDA SSA These pins are the power supplies for the analog circuitry of the ATD block. 160 is the low reference voltage for ATD conversion. RL — Power Supply Pins MC9S12XDP512 Data Sheet, Rev. 2.17 before initiating a new ATD SR Freescale Semiconductor ...
Page 161
... Trigger Mode and Mux Timing Control ATDDIEN PORTAD Successive Approximation Register (SAR) and DAC Sample & Hold 1 Analog MUX Figure 5-1. ATD Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 ATD10B8C Sequence Complete Interrupt Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 + – ...
Page 162
... AFFC AWAI ETRIGLE S8C S4C S2C SMP1 SMP0 PRS4 DSGN SCAN MULT 0 ETORF FIFOR Unimplemented or Reserved MC9S12XDP512 Data Sheet, Rev. 2. WRAP2 WRAP1 0 ETRIGCH2 ETRIGCH1 ETRIGCH0 ETRIGP ETRIGE ASCIE S1C FIFO FRZ1 PRS3 PRS2 PRS1 CC2 ...
Page 163
... BIT 8 BIT 7 BIT 6 BIT 6 BIT 5 BIT 4 BIT BIT 8 BIT 7 BIT 6 BIT 6 BIT 5 BIT 4 = Unimplemented or Reserved MC9S12XDP512 Data Sheet, Rev. 2. CCF3 CCF2 CCF1 IEN3 IEN2 IEN1 PTAD3 PTAD2 PTAD1 BIT 5 BIT 4 BIT 3 BIT 3 BIT 2 BIT ...
Page 164
... BIT Right Justified Result Data Section 5.3.2.13, “ATD Conversion Result Registers BIT 6 BIT 5 BIT 4 BIT 6 BIT 5 BIT 4 = Unimplemented or Reserved MC9S12XDP512 Data Sheet, Rev. 2. BIT 5 BIT 4 BIT 3 BIT 3 BIT 2 BIT ...
Page 165
... BIT 6 BIT 5 BIT 4 BIT 6 BIT 5 BIT BIT 6 BIT 5 BIT 4 BIT 6 BIT 5 BIT 4 = Unimplemented or Reserved MC9S12XDP512 Data Sheet, Rev. 2. BIT 9 MSB BIT 3 BIT 2 BIT 1 BIT 3 BIT 2 BIT BIT 9 MSB BIT 3 BIT 2 BIT 1 ...
Page 166
... Table 5-1. ATDCTL0 Field Descriptions Description Multiple Channel Conversions (MULT = 1) WRAP1 WRAP0 Wrap Around to AN0 after Converting MC9S12XDP512 Data Sheet, Rev. 2. BIT 9 MSB BIT 3 BIT 2 BIT 1 BIT 3 BIT 2 BIT WRAP2 WRAP1 ...
Page 167
... X X MC9S12XDP512 Data Sheet, Rev. 2. ETRIGCH2 ETRIGCH1 Table 5-4. External trigger source is AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 1 ETRIG0 1 ETRIG1 1 ETRIG2 1 ETRIG3 Reserved ...
Page 168
... Note: If using one of the AD channel as external trigger (ETRIGSEL = 0) the conversion results for this channel have no meaning while external trigger mode is enabled. 168 AWAI ETRIGLE ETRIGP Table 5-5. ATDCTL2 Field Descriptions Description Table 5-4. If external trigger source is one of the AD channels, the digital MC9S12XDP512 Data Sheet, Rev. 2. ASCIF ETRIGE ASCIE Table 5-6 for Freescale Semiconductor ...
Page 169
... Table 5-6. External Trigger Configurations ETRIGP External Trigger Sensitivity S4C S2C 0 0 Table 5-7. ATDCTL3 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2.17 Falling edge Rising edge Low level High level S1C FIFO FRZ1 Table 5-8 0 FRZ0 0 shows ...
Page 170
... FRZ0 Behavior in Freeze Mode 0 Continue conversion 1 0 Finish current conversion, then freeze 1 Freeze Immediately MC9S12XDP512 Data Sheet, Rev. 2.17 Number of Conversions per Sequence Reserved Freescale Semiconductor ...
Page 171
... Table 5-11. Sample Time Select SMP0 Length of 2nd Phase of Sample Time 0 2 A/D conversion clock periods 1 4 A/D conversion clock periods 0 8 A/D conversion clock periods 1 16 A/D conversion clock periods MC9S12XDP512 Data Sheet, Rev. 2. PRS2 PRS1 PRS0 1 171 ...
Page 172
... Divide by 54 108 MHz Divide by 56 112 MHz Divide by 58 116 MHz Divide by 60 120 MHz Divide by 62 124 MHz Divide by 64 128 MHz MC9S12XDP512 Data Sheet, Rev. 2. Min. Bus Clock 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz ...
Page 173
... Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3 SCAN MULT Table 5-13. ATDCTL5 Field Descriptions Description Section 5.3.2.13, “ATD Conversion Result Registers (ATDDRx),” Table 5-16 lists the coding used to select the various analog input MC9S12XDP512 Data Sheet, Rev. 2. for details. 173 ...
Page 174
... MC9S12XDP512 Data Sheet, Rev. 2.17 Signed Unsigned 10-Bit 10-Bit Codes Codes 7FC0 FFC0 7F00 FF00 7E00 FE00 0100 8100 0000 8000 FF00 7F00 8100 0100 8000 0000 Analog Input Channel ...
Page 175
... Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3 ETORF FIFOR Table 5-17. ATDSTAT0 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. CC2 CC1 CC0 175 ...
Page 176
... Table 5-18. ATDTEST1 Field Descriptions Description Table 5-19 lists the coding. Table 5-19. Special Channel Select Coding MC9S12XDP512 Data Sheet, Rev. 2. Analog Input Channel Reserved V RH ...
Page 177
... will be overwritten by the set. 0 Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3 CCF5 CCF4 CCF3 Table 5-20. ATDSTAT1 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. CCF2 CCF1 CCF0 177 ...
Page 178
... IEN4 IEN3 0 0 Table 5-21. ATDDIEN Field Descriptions Description 5 4 PTAD5 PTAD4 PTAD3 1 1 AN5 AN4 AN3 Figure 5-14. Port Data Register (PORTAD) Table 5-22. PORTAD Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. IEN2 IEN1 PTAD2 PTAD1 AN2 AN1 or V specifi ...
Page 179
... BIT 5 BIT 4 BIT 3 BIT 5 BIT 4 BIT MC9S12XDP512 Data Sheet, Rev. 2. BIT 4 BIT 3 BIT 2 BIT 2 BIT 1 BIT BIT 9 MSB ...
Page 180
... The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range non-railed digital output codes. 180 allow to isolate noise of other MCU circuitry from the analog sub-block MC9S12XDP512 Data Sheet, Rev. 2. SSA DDA (A/D reference potentials) will result RH Freescale Semiconductor . ...
Page 181
... X Rising edge triggered. Performs one conversion sequence per trigger Trigger active low. Performs continuous conversions while trigger is active Trigger active high. Performs continuous conversions while trigger is active. NOTE MC9S12XDP512 Data Sheet, Rev. 2.17 Description 181 ...
Page 182
... Sequence complete See register descriptions for further details. 182 Table 5-24. Refer to the device overview chapter for related Table 5-24. ATD Interrupt Vectors CCR Mask I bit ASCIE in ATDCTL2 interrupt MC9S12XDP512 Data Sheet, Rev. 2.17 Definition”), which details the registers Local Enable Freescale Semiconductor ...
Page 183
... A 7-bit identifier associated with an XGATE channel. In S12X designs valid Channel IDs range from $78 to $09. XGATE Channel Interrupt An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module. XGATE Software Channel Freescale Semiconductor (Section 6.4.4, “Semaphores”) “Interrupts”) Mode”) Set”) MC9S12XDP512 Data Sheet, Rev. 2.17 Definition”) Core”) 183 ...
Page 184
... There are four run modes on S12X devices. • Run mode, wait mode, stop mode The XGATE is able to operate in all of these three system modes. Clock activity will be automatically stopped when the XGATE module is idle. • Freeze mode (BDM active) 184 MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 185
... Peripheral Interrupts XGATE Software Triggers Peripherals 6.2 External Signal Description The XGATE module has no external pins. Freescale Semiconductor S12X_INT Interrupt Flags Semaphores RISC Core Software Triggers S12X_MMC Figure 6-1. XGATE Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 6 XGATE (S12XGATEV2) (XGMCTL)”). S12X_DBG 185 ...
Page 186
... Figure 6-2. XGATE Register Summary (Sheet 186 Figure XGE XGFRZ XGDBG XGSS XG XG XGIEM SWEIFM FACTM 0 XGVBR[15:1] MC9S12XDP512 Data Sheet, Rev. 2.17 6-2.The address listed for each register FACT SWEIF XGCHID[6:0] Freescale Semiconductor 0 XGIE 0 ...
Page 187
... MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 6 XGATE (S12XGATEV2) 118 117 116 115 114 102 101 100 ...
Page 188
... Unimplemented or Reserved Figure 6-2. XGATE Register Summary (Sheet 188 XGPC XGR1 XGR2 XGR3 XGR4 XGR5 XGR6 XGR7 MC9S12XDP512 Data Sheet, Rev. 2. XGSWT[7:0] XGSEM[7: XGN XGZ XGV XGC Freescale Semiconductor 0 ...
Page 189
... Enable write access to the XGSS in the same bus cycle Freescale Semiconductor XGE XGFRZ XGDBG XGSS XGFACT XG XG XGIEM FACTM SWEIFM Description MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 6 XGATE (S12XGATEV2) Figure 6- SWEIF XGIE 0 0 189 ...
Page 190
... RISC core is not in Debug Mode 1 RISC core is in Debug Mode Write: 0 Leave Debug Mode 1 Enter Debug Mode Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit. 190 Description MC9S12XDP512 Data Sheet, Rev. 2.17 Section 6.6, “Debug Mode”). Freescale Semiconductor ...
Page 191
... XGATE Interrupt Enable — This bit acts as a global interrupt enable for the XGATE module XGIE Read: 0 All XGATE interrupts disabled 1 All XGATE interrupts enabled Write: 0 Disable all XGATE interrupts 1 Enable all XGATE interrupts Freescale Semiconductor Description Section 6.4.5, “Software Error MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 6 XGATE (S12XGATEV2) Detection”). The RISC core is stopped while 191 ...
Page 192
... XGCHID[6: Table 6-2. XGCHID Field Descriptions Description (Figure 6-5 and Figure 6-6) determines the location of the XGATE vector XGVBR[15: Table 6-3. XGVBR Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...
Page 193
... MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 6 XGATE (S12XGATEV2) 118 117 116 115 114 102 101 100 ...
Page 194
... Suggested Mnemonics for accessing the interrupt flag vector on a word basis are: XGIF_7F_70 (XGIF[127:112]), XGIF_6F_60 (XGIF[111:96]), XGIF_5F_50 (XGIF[95:80]), XGIF_4F_40 (XGIF[79:64]), XGIF_3F_30 (XGIF[63:48]), XGIF_2F_20 (XGIF[47:32]), XGIF_1F_10 (XGIF[31:16]), XGIF_0F_00 (XGIF[15:0]) 194 Table 6-4. XGIV Field Descriptions Description NOTE MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor ...
Page 195
... XGATE requests as well as S12X_CPU interrupts. The target of the software trigger must be selected in the S12X_INT module. Freescale Semiconductor Table 6-5. XGSWT Field Descriptions Description NOTE MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 6 XGATE (S12XGATEV2 XGSWT[7: 195 ...
Page 196
... Clear semaphore if it was locked by the S12X_CPU 1 Attempt to lock semaphore by the S12X_CPU 196 for details “Semaphores”) Table 6-6. XGSEM Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. XGSEM[7: Freescale Semiconductor ...
Page 197
... Overflow Flag — The RISC core’s Overflow flag XGV 0 Carry Flag — The RISC core’s Carry flag XGC Freescale Semiconductor XGN Table 6-7. XGCCR Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 6 XGATE (S12XGATEV2 XGZ XGV XGC 197 ...
Page 198
... XGPC Figure 6-11. Table 6-8. XGPC Field Descriptions Description XGR1 Figure 6-12. XGATE Register 1 (XGR1) Table 6-9. XGR1 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...
Page 199
... Figure 6-13. XGATE Register 2 (XGR2) Table 6-10. XGR2 Field Descriptions Description XGR3 Figure 6-14. XGATE Register 3 (XGR3) Table 6-11. XGR3 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2.17 Chapter 6 XGATE (S12XGATEV2 ...
Page 200
... Figure 6-15. XGATE Register 4 (XGR4) Table 6-12. XGR4 Field Descriptions Description XGR5 Figure 6-16. XGATE Register 5 (XGR5) Table 6-13. XGR5 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...