BT861KRF Conexant Systems, Inc., BT861KRF Datasheet
BT861KRF
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BT861KRF Summary of contents
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Bt860/861 Multiport YCrCb to NTSC / PAL / SECAM Digital Video Encoder The Bt860/861 is a multiport digital video encoder with pixel synchronization and per-pixel blending capabilities. The three 8-bit YCrCb data ports allow for a variety of video and ...
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... Ordering Information Model Number Bt860KRF Bt861KRF Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products ...
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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.0 Digital Processing and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 4.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents vi Multiport YCrCb to NTSC/PAL /SECAM Conexant Bt860/861 D860DSA ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM List of Figures Figure 1-1. Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures viii Multiport YCrCb to NTSC/PAL /SECAM Conexant Bt860/861 D860DSA ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM List of Tables Table 1-1. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables x Multiport YCrCb to NTSC/PAL /SECAM Conexant Bt860/861 D860DSA ...
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Functional Description 1.1 Pin Descriptions Figure 1-1. Pinout Diagram VIDCLK VIDVALID VIDVACT VIDHACT VDDMAX D860DSA 1 VID2 1 VID3 2 VID4 3 VID5 4 VID6 5 VID7 6 VDD 80-pin MQFP ...
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Functional Description 1.1 Pin Descriptions Table 1-1. Pin Assignments ( Pin Name I/O Pin # P[7:0] I 22-19, 16-13 CLKO O 70 VSYNC* I/O 24 HSYNC* I/O 25 BLANK FIELD O 26 VID[7:0] I 6-1, ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Table 1-1. Pin Assignments ( Pin Name I/O Pin # OSD[7:0] I 40-39, 36-31 ALPHA[1:0] I 30-29 TELETEXT AND SERIAL CONTROL INTERFACE TTXDAT I 74 TTXREQ O 73 ALTADDR I/O 62 SID ...
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Functional Description 1.1 Pin Descriptions Table 1-1. Pin Assignments ( Pin Name I/O Pin # CLKIN I 71 RESET XTI I 67 XTO O 68 VAA 55, 46, 52 — VDD — 7, 28, 38, ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 1.2 Functional Overview The Bt860/861 is a highly programmable 3.3 V multiport digital video encoder with pixel synchronization and per-pixel blending capabilities equipped with three 8-bit YCrCb data ports that allow a ...
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Functional Description 1.2 Functional Overview Figure 1-2. Detailed Block Diagram 1-6 Multiport YCrCb to NTSC/PAL /SECAM Conexant Bt860/861 861_028 D860DSA ...
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Inputs and Timing 2.1 Reset The Bt860/Bt861 has the following reset methods: • power-up reset • RESET* pin reset • software reset register bit Power-up reset occurs when the part is powered-up. A pin reset occurs when the RESET* ...
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Inputs and Timing 2.2 Digital Video Ports 2.2 Digital Video Ports Internally, data to the Bt860/861 is treated as either video, overlay, or alpha data. Video data is the primary visual program content, while overlay data is used for ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 2.2.1 The P Port The P port can accept video data from a variety of digital video sources designed specifically to interface directly with commercial MPEG video decoders and D1 digital video ...
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Inputs and Timing 2.2 Digital Video Ports 2.2.4 Overlay Modes and Alpha Blending The Bt860/861 can be configured to display only a single video stream mix any combination of two data ports (P, VID, and OSD). Programming ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 2.2.5 Alpha Pin Blending The ALPHA[1:0] pins are used to select the amount of blending per pixel when BLENDMODE = 1. The pins are sampled at the system clock rate and samples during both ...
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Inputs and Timing 2.3 Configurations and Timing 2.3 Configurations and Timing The Bt860/861 is capable of various ITU-R BT.601, ITU-R BT.656, and decoder-locked configurations. ITU-R BT.656 configurations, and configurations. In any of these configurations possible to synchronize ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 2.3.1 ITU-R BT.601 Configurations and Timing Master and slave ITU-R BT.601 configurations are listed in modes 1 and 2. Timing mode 1 is the ITU-R BT.601 master mode. An example connection diagram is illustrated ...
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Inputs and Timing 2.3 Configurations and Timing Timing mode 2 is the ITU-R BT.601 slave mode. An example connection diagram is illustrated in is the timing master, and both the optional OSD source and the Bt860/861 are timing slaves. ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM If the registers are used to determine video blanking (register bit BLK_IGNORE = 1), the first component of the first active pixel of a line should be presented to the encoder at HBLANK + ...
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Inputs and Timing 2.3 Configurations and Timing The HBLANK register sets the line blanking time from the midpoint of the falling edge of the analog horizontal sync pulse to the end of blanking. The HACTIVE register sets the number ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Figure 2-7. 625 Line ITU-R BT.656 Timing Analog Line n – 1 Digital Line n – 1 Luminance Samples 717 718 719 720 721 Cr Samples 359 360 Cb Samples 359 360 T : ...
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Inputs and Timing 2.3 Configurations and Timing In this configuration, the Bt860/861 is a slave to the ITU-R BT.656 data stream. However, the HSYNC*, VSYNC* and FIELD pins can be configured as outputs for synchronization with a video slave ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Figure 2-9. Video Decoder Connection Example Bt835 Video Decoder MPEG-2 Decoder Graphic Processor Follow these steps to lock a video decoder to this port NOTE: D860DSA 8 VD[15:8] VID[7:0] ...
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Inputs and Timing 2.4 Clock Selection 2.4 Clock Selection The internal pixel clock (PCLK) can be derived from either the CLKIN input or the crystal inputs. The PCLK_SEL register bit (19[7]) controls which of these two inputs will become ...
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Digital Processing and Functionality 3.1 Video 3.1.1 Video Standards The Bt860/861 supports worldwide video standards, including NTSC-M (N. America, Taiwan, Japan), PAL- (Europe, Asia), PAL-M (Brazil), PAL-N (Uruguay, Paraguay), PAL-Nc (Argentina), PAL-60, NTSC-443, and SECAM. ...
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Multiport YCrCb to NTSC/PAL /SECAM Conexant Bt860/861 D860DSA ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM D860DSA Conexant 3-3 ...
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Multiport YCrCb to NTSC/PAL /SECAM Conexant Bt860/861 D860DSA ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM D860DSA Conexant 3-5 ...
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Multiport YCrCb to NTSC/PAL /SECAM Conexant Bt860/861 D860DSA ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM D860DSA Conexant 3-7 ...
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Table 3-4. Register Programming Values for SECAM Parameter Description Number of Lines Width of Analog Horizontal Sync Pulse Cross Color Filtering Off Upper Db Limit Lower Db Limit Upper Dr Limit Lower Dr Limit Bottleneck Pulses FM Modulation Number ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 3.1.2 Analog Horizontal Sync The duration of the horizontal sync pulse is determined by register HSYNC_WIDTH (12[7:0]). The beginning of the horizontal sync pulse corresponds to the reset of the internal horizontal pixel counter. ...
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Digital Processing and Functionality 3.1 Video Figure 3-2. PAL Vertical Timing NOTE(S): (1) Internal timing considers this point the start of the field (vertical reset). 3.1.4 Analog Video Blanking In master mode, and when register bit BLK_IGNORE = 1 ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 3.1.5 Subcarrier and Burst Generation The Bt860/861 uses a 32-bit subcarrier increment to synthesize the subcarrier. The value of the subcarrier increment required to generate the desired subcarrier frequency for NTSC and PAL formats ...
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Digital Processing and Functionality 3.1 Video 3.1.6 Subcarrier Phasing (SC_H Phase) For PAL and NTSC video formats, the subcarrier phase is set the leading edge of the analog vertical sync every four (NTSC) or eight (PAL) ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 3.2 Effects 3.2.1 Chrominance Disable Setting register bit DCHROMA (17[2 turns off the chrominance subcarrier and colorburst. 3.2.2 Internal Filtering Once the input data is converted to internal YUV format, the Y ...
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Digital Processing and Functionality 3.2 Effects Figure 3-5. Close-Up of Luminance Upsampling Filter with Peaking and Reduction Options 0 –5 –10 –15 – Frequency in MHz Figure 3-7. Luminance Peaking Filter Options 4 ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Figure 3-11. SECAM Low Frequency Pre-emphasis Filter 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Frequency in MHz 3.2.3 Internal Colorbars, Blue Field, and Black Burst The Bt860/861 ...
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Digital Processing and Functionality 3.2 Effects Figure 3-12. YUV Video Format (Internal Colorbars) A sync y V(Pb) U(Pr) All “A “ values are relative to black, except for A NOTE(S): x Table 3-5. 100/0/75/0 Colorbars as Described in EIA-770.1. ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Figure 3-13. RGB Video Format (Internal Colorbars All “A “ values are relative to black, except for A NOTE(S): x Table 3-6. 100/0/75/0 Colorbars for a 625-Line System ( ...
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Digital Processing and Functionality 3.2 Effects Figure 3-14. Composite and S-Video Format (Internal Colorbars) A sync Composite A sync y S Video C NOTE(S the DC (luminance) amplitude referenced to black, except for ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Table 3-8. Composite and Chrominance Magnitude C and Composite wht Magnitudes NTSC-M (volts) 0.286 0 NTSC-J (volts) 0.286 0 PAL-B (volts) 0.300 0 M numbers are the peak-to-peak amplitudes of the ...
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Digital Processing and Functionality 3.2 Effects 3.2.7 Programmable Video Adjustments Controls Registers Y_OFF, M_Y, M_CB, M_CR, and PHASE_OFF program video adjustment controls for hue, brightness, contrast, saturation, and sharpness. 3.2.7.1 Hue Adjust There are two methods for adjusting the ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 3.2.7.3 Contrast Adjust Register M_Y (22[7:0]) controls contrast adjustment. This modifies the luminance multiplier, allowing a larger or smaller luminance range. 3.2.7.4 Saturation Registers M_CB (21[7:0]) and M_CR (20[7:0]) control saturation adjustments. Adjust These ...
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Digital Processing and Functionality 3.2 Effects 3.2.8 Macrovision Encoding (Bt861 Only) The anticopy process contained within the Bt861 is implemented according to the version 7.x. Specification, developed by Macrovision Corporation in Sunnyvale, California. The Macrovision Anticopy process is available ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 3.2.11 Special SCART Signals At power-up, the ALTADDR pin is sampled to determine the Bt860/861’s serial programming address. At all other times the SCART_SEL (3C[1:0]) register field determines its function. Setting the SCART_SEL register ...
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Digital Processing and Functionality 3.2 Effects 3.2.13 Output Filtering and SINX/X Compensation The DAC output response is a typical sinx/x response. For the composite video output, this results in slightly lower than desired burst and chroma amplitude values. To ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 3.2.15 Teletext Operation of Bt860/861 Teletext encoding in the Bt860/861 is accomplished via a two-wire interface, TTXDAT and TTXREQ, and several control registers, programmed via the serial programming interface. The Bt860/861 Teletext output conforms ...
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Digital Processing and Functionality 3.2 Effects 3.2.15.1 Teletext Timing Setting register bit TXRM to 1 puts the Bt860/861 in Teletext timing mode 1. In Mode 1 this mode, the TTXDAT pin is the Teletext data entry pin, and the ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 3.2.15.3 General A logical 1 on the TTXDAT pin corresponds to an analog output value of 66% of Teletext Operation the black-to-white transition (approximately 462 mV above black), and a logical 0 corresponds to ...
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Digital Processing and Functionality 3.2 Effects Figure 3-18 Note that WSS uses bi-phase coding of its data bits. The amplitude of the WSS pulses is 500 mV above black when high, and black when low. For further WSS details, ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM CRC data is not calculated and must be provided by the user. illustrates a typical CGMS signal. Note that bit 1 is closest to the HSYNC pulse and bit 20 is farthest. The amplitude ...
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Digital Processing and Functionality 3.2 Effects The ECCGATE register bit must be 1 for normal operation. When this bit is set to 1, current data is displayed for one frame, and then the NULL data sequence is displayed until ...
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Applications 4.1 PC Board Considerations The layout for the Bt860/861 should be optimized for the lowest noise possible on the power and ground planes by providing good decoupling. The trace length between groups of power and ground pins should ...
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Applications 4.1 PC Board Considerations Figure 4-1. Typical Connection Diagram ( VDD VDDMAX VAA COMP 1 COMP 2 VBIAS 1 VBIAS 2 VREF GND AGND FSADJ 1 FSADJ 2 DACA DACB DACB DACB DACB DACB LPF C18 ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 4.1.3 Device Decoupling For optimum performance, all decoupling capacitors should be located as close as possible to the device, and the shortest possible leads should be used to reduce the lead inductance. Chip capacitors ...
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Applications 4.1 PC Board Considerations Table 4-1. Typical Parts List Location C1, C15 C16 C17 C18 C19 C2 C20 C3– load RSET1, RSET2 TRAP XTAL NOTE(S): characteristics will not affect BT860/861 performance. 4.1.5 COMP ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 4.1.8 Digital Signal Interconnect The digital inputs to the Bt860/861 should be isolated from the analog outputs and other analog circuitry as much as possible and should not overlay the analog power plane. Most ...
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Applications 4.1 PC Board Considerations 4-6 Multiport YCrCb to NTSC/PAL /SECAM Conexant Bt860/861 D860DSA ...
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Serial Programming Interface and Registers 5.1 Serial Interface The Bt860/861 uses a 2-wire serial programming interface to program the device registers. The interface operates at 3 5.0 V input levels. illustrates the timing relationship between Serial Interface ...
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Serial Programming Interface and Registers 5.1 Serial Interface Every data word put onto the SID line must be 8 bits long (MSB first), followed by an acknowledge bit, generated by the receiving device. Each data transfer is initiated with ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Figure 5-2. Serial Programming Interface Typical Write Sequence Chip Write S Address 5.1.3 Reading Data A read transaction involves sending the device address byte with the read/write* bit high, and receiving ...
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Serial Programming Interface and Registers 5.2 Internal Registers 5.2 Internal Registers Registers provide direct control and status of the part. These registers are accessed by the serial programming interface described in this section. provides a register bit map. Section ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Table 5-2. Register Bit Map ( Sub Default D7 D6 (1) addr Values 15 0F PLL_FRACT [18:16 SC_RESET VSYNC_DUR 625LINE CHROMA_BW BLUE_FLD YDELAY[2: PCLK_SEL ...
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Serial Programming Interface and Registers 5.2 Internal Registers Table 5-2. Register Bit Map ( Sub Default D7 D6 (1) addr Values 36 04 (4) Reserved 37 00 Y_OFF[7: PHASE_OFF[7: ALPHA_LUT_1[3: ALPHA_LUT_3[3:0] ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Table 5-2. Register Bit Map ( Sub Default D7 D6 (1) addr Values 59 02 (4) Reserved 5A 00 TTX_DIS[7: TTX_DIS[15: MULT_UU[7: MULT_VU[7:0] MULT_UV[7: ...
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Serial Programming Interface and Registers 5.3 Register Index 5.3 Register Index Table 5-3. Register Index ( Default Field (1) Value 625LINE 0 AHSYNC_WIDTH[7:0] 7E ALPHA_LUT_0[3: ALPHA_LUT_1[3:0] A ALPHA_LUT_2[3:0] F ALPHA_LUT_3[3:0] ALPHAMODE[1:0] 00 AUTO_CHK 0 BLANKI ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Table 5-3. Register Index ( Default Field (1) Value DR_MAX[10:0] 5A3 DR_MIN[10:0] 49F EACTIVE 0 ECBAR 0 ECC 0 ECCGATE 0 ECLIP 0 EN_656 0 EN_DAC_A 1 1 EN_DAC_B 1 EN_DAC_C 1 ...
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Serial Programming Interface and Registers 5.3 Register Index Table 5-3. Register Index ( Default Field (1) Value LC_FIFOWIN[8:0] 180 LC_MAXOFF[7:0] 80 LC_RST 1 LOCK 0 M_CB[7:0] 89 M_COMP_D[7:0] 80 M_COMP_F[7:0] M_COMP_E[7:0] M_CR[7:0] C1 M_SC_DB[31:0] 284BDA13 M_SC_DR[31:0] 21F07C1F ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Table 5-3. Register Index ( Default Field (1) Value SC_AMP[7:0] 85 SC_PATTERN 0 SC_RESET 0 SCART_SEL 00 SETUP 1 SLAVE 0 SLEEP 0 SQUARE 0 SRESET 0 SYNC_AMP[7:0] E5 SYNC_CFG 0 TTX_DIS[15:0] ...
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Serial Programming Interface and Registers 5.3 Register Index Table 5-3. Register Index ( Default Field (1) Value WSDAT[20:1] — XDS_STAT — XDSB1[7:0] 80 XDSB2[7:0] 80 XDSSEL[3:0] 4 XL_GAIN[3:0] 7 XL_LOCK 1 XL_MDSEL[1:0] 01 XL_SAT[3:0] 2 XL_SATEN 0 ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 5.4 Register Detail NOTE(S): (1) Internal timing and the values programmed into the registers reference the analog VSYNC pulse (O 2. System clock = luminance sample frequency. CLK Register 00 Default ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 02 Default Register D7 D6 Value 02 04 FIELD_CNT[3:0] This register is read only. Field Number FIELD_CNT[3:0] 000 indicates the first field. VLOCK_ERR VID Port Locking Status High if VID ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 08 Default Register D7 D6 Value 08 7E Analog Horizontal Sync Width AHSYNC_WIDTH[7:0] Measured in system clock cycles, from 50% points of sync pulse. Register 09 Default Register D7 D6 Value 09 90 ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 0B–0C Default Register D7 D6 Value Reserved bits should be set to zero when written and will return zero when read. HBLANK[9:0] Horizontal Blanking Length Determines ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 10–11 Default Register D7 D6 Value Reserved bits should be set to zero when written and will return zero when read. HSYNC_OFF[9:0] HSYNC* Offset Defines the offset in system ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 16 Default Register D7 D6 Value 16 10 SC_RESET VSYNC_DUR Subcarrier Reset SC_RESET 0 = Subcarrier phase reset at beginning of each color field sequence Disable subcarrier reset. ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 17 Default Register D7 D6 Value 17 10 CHROMA_BW BLUE_FLD Chrominance Bandwidth CHROMA_BW 0 = Normal chroma bandwidth Wide chroma bandwidth. See filter plots in Blue Field BLUE_FLD 0 = Normal ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 18 Default Register D7 D6 Value 18 3F YDELAY[2:1] MSBs of Luma Delay in Pixels for CVBS_DLY Outputs YDELAY[2:1] YDELAY[ 1/2 pixel increments, at 3C[6 ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 19 Default Register D7 D6 Value 19 80 PCLK_SEL VSYNCI Pixel Clock (system clock) Select PCLK_SEL State of FIELD pin during power-up determines the default value of PCLK_SEL. FIELD = 1 corresponds to ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 1A Default Register D7 D6 Value 1A 80 BLENDMODE ALPHAMODE[1:0] Blend Select BLENDMODE 0 = Alpha control contained in Y[1:0] of port selected by OVRLAY_SEL Alpha control contained ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 1B Default Register D7 D6 Value 1B 00 SRESET FIELD_ID Software Reset SRESET 0 = Normal operation Reset all serial programming registers to their default values. Enable SECAM Bottleneck Pulses FIELD_ID ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 1C Default Register D7 D6 Value 1C C1 XL_VRI LC_RST Accelerated Locking Vertical Realignment Initiation XL_VRI 0 = Disable Accelerated Locking Vertical Realignment Initiation Enable Accelerated Locking Vertical ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 1D Default Register D7 D6 Value 1D 01 DIS_XTAL DIS_SCADJ Disable Crystal Circuitry DIS_XTAL 0 = Normal operation Power down crystal oscillator circuitry. Disable Automatic Subcarrier Adjust DIS_SCADJ 0 = Normal ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 1F Default Register D7 D6 Value 1F 75 Multiplication Factor for the Colorburst Amplitude for NTSC/PAL BURST_AMP[7:0] This register is ignored when using SECAM. BURST_AMP = int {BURST BURST_AMP = ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 23–25 Default Register D7 D6 Value M_COMP_D[7:0] Multiplication Factor for the Component at DAC D Multiplication Factor for the Component at DAC F M_COMP_F[7:0] Multiplication Factor for ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 2E Default Register D7 D6 Value 2E 85 Multiplication Factor for the SECAM Subcarrier Amplitude SC_AMP[7:0] Measured in LSB increments. SC_AMP = (Amp where Amp SincX = Sin[( × F ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 33–34 Default Register D7 D6 Value Reserved bits should be set to zero when written and will return zero when read. DB_MAX[10:0] Upper Boundary for Db Frequency Deviation in ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 39–3A Default Register D7 D6 Value 39 50 ALPHA_LUT_1[3: ALPHA_LUT_3[3:0] ALPHA_LUT_0[3:0] Alpha Blend Lookup Table Element 0 Alpha Blend Lookup Table Element 1 ALPHA_LUT_1[3:0] Alpha Blend Lookup Table ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 3C Default Register D7 D6 Value 3C 10 VIDCLK_EDGE YDELAY[0] VIDCLK EDGE Sample Select VIDCLK_EDGE 0 = VID[7:0], VIDHACT, VIDVALT, VIDFIELD, VIDVALID are sampled on the rising edge of the VIDCLK ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 42–43 Default Register D7 D6 Value CCB1[7:0] First Byte of Closed Data is encoded LSB first. Second Byte of Closed CCB2[7:0] Data is encoded LSB first. ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 48 Default Register D7 D6 Value 48 00 Reserved bits should be set to zero when written and will return zero when read. Closed Captioning Gating ECCGATE 0 = After current CC/XDS data ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 4A–4C Default Register D7 D6 Value 4A — EWSSF2 EWSSF1 4B — 4C — Reserved bits should be set to zero when written and will return zero when read. Enable ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 4F–50 Default Register D7 D6 Value Reserved bits should be set to zero when written and will return zero when read. TTXHE[10:0] TTXREQ Falling Edge Number of clocks from ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 55–56 Default Register D7 D6 Value Reserved bits should be set to zero when written and will return zero when read. TTXBF2[8:0] Teletext Start Line for ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Register 5A–5B Default Register D7 D6 Value Reserved bits should be set to zero when written and will return zero when read. Teletext Disable by Line TTX_DIS[15: ...
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Serial Programming Interface and Registers 5.4 Register Detail Register 70–71 Default Register D7 D6 Value Reserved bits should be set to zero when written and will return zero when read. FIFO Window LC_FIFOWIN[8:0] Defines the ...
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Parametric Data and Specifications 6.1 Electrical Specifications 6.1.1 Electrical Parameters Table 6-1. Absolute Maximum Ratings Parameter VAA, VDD (measured to GND) (1) Voltage on Any Signal Pin Analog Output Short Circuit Duration to Any Power Supply or Common Storage ...
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Parametric Data and Specifications 6.1 Electrical Specifications Table 6-2. DC Characteristics Parameter Output Current-DAC Code 1023 (I Full Scale) OUT Output Voltage-DAC Code 1023 Video Level Error (Nominal Resistors) DAC Output Capacitance Digital Inputs (Except SID, SIC) Input High ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM Figure 6-1. Pixel and Control Data Timing Diagram System Clock t 1 HSYNC* VSYNC* Input BLANK* Timing OSD[7:0] P[7:0] Output HSYNC* Timing VSYNC* FIELD Table 6-3. AC Characteristics Parameter (1) CLKIN Frequency CLKIN Pulse ...
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Parametric Data and Specifications 6.1 Electrical Specifications Table 6-4. Video Quality Specifications Parameter Differential Phase NTC-7 Composite Differential Gain NTC-7 Composite Chrominance Nonlinear Gain NTC-7 Combination, Referenced to 40 IRE Chrominance Nonlinear Phase NTC-7 Combination, Referenced to 40 IRE ...
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Bt860/861 Multiport YCrCb to NTSC/PAL /SECAM 6.2 Mechanical Drawing Figure 6-2. 80 MQFP Package Diagram 80 MQFP - 1.6/0.15mm FORM TOP VIEW SIDE VIEW DETAIL D860DSA ...
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Parametric Data and Specifications 6.2 Mechanical Drawing 6-6 Multiport YCrCb to NTSC/PAL /SECAM Conexant Bt860/861 D860DSA ...
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... India Web Site Phone: (91 11) 692 4780 www.conexant.com Fax: (91 11) 692 4712 World Headquarters Korea Conexant Systems, Inc. Phone: (82 2) 565 2880 Fax: (82 2) 565 1440 4311 Jamboree Road P. O. Box C Phone: (82 53) 745 2880 Newport Beach, CA Fax: (82 53) 745 1440 ...