LXT6234QE Intel Corporation, LXT6234QE Datasheet

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LXT6234QE

Manufacturer Part Number
LXT6234QE
Description
Manufacturer
Intel Corporation
Datasheet

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LXT6234
E-Rate Multiplexer
The LXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary
channels into a single high speed data stream and for demultiplexing a high speed data stream
back to four tributary channels. All of the necessary circuitry is integrated into the LXT6234 E-
Rate Multiplexer; there is no need for an external framing device.
The LXT6234 E-Rate Multiplexer conforms to both the (ITU) G.742 and (ITU) G.751
multiplexing formats defined by the International Telecommunications Union (ITU; formerly
known as CCITT): G.742 recommendation for multiplexing four E1 channels into an E2 frame;
and the G.751 recommendation for multiplexing four E2 channels into an E3 frame.
The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding
used on E1, E2, and E3 signals. The coder and decoder input/output pins are externally
accessible, allowing either HDB3 or NRZ (non-return-to-zero) I/O to the multiplexer. The
LXT6234 E-Rate Multiplexer can also serve as a five channel HDB3 coder and decoder.
Applications
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Product Features
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As of January 15, 2001, this document replaces the Level One document
LXT6234 E-Rate Multiplexer Datasheet.
E1/E2 Multiplexer (2/8 Mbit/s)
E2/E3 Multiplexer (8/34 Mbit/s)
E1/E3 Multiplexer (2/34 Mbit/s)
Performs four-E1 to one-E2, or four-E2 to
one-E3 multiplexing. Five ICs will
implement a sixteen-E1 to one-E3
multiplexer.
Fully compliant with the G.742 and G.751
ITU recommendations. Fully compliant
with G.703 when used with LXT305/332
Line Interface.
A robust frame-acquisition and frame-
holding algorithm minimizes frame
slippage, acquires and holds frame below
10
-2
bit error rate.
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Digital Loop Carrier (DLC) Terminal
Add / Drop Multiplexers (ADM)
4 - to - 1 Non-Standard Multiplexer
Four auxiliary low speed data or flag
channels are available via the Stuffing Bits
on each tributary channel.
Access to the Alarm bit and the National
bit. These can be used as recommended by
ITU or for proprietary use.
Five independent HDB3 CODECs allow
multiplexer I/O in either HDB3 or NRZ
formats. The LXT6234 can also function as
a stand alone five-channel HDB3
transcoder.
Order Number: 249301-001
Datasheet
January 2001

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LXT6234QE Summary of contents

Page 1

LXT6234 E-Rate Multiplexer The LXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary channels into a single high speed data stream and for demultiplexing a high speed data stream back to four tributary channels. All of the necessary ...

Page 2

... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ® ...

Page 3

Contents 1.0 Block Diagram 2.0 Conscription ................................................................................................................. 6 3.0 Functional Description 3.1 Frame Format......................................................................................................11 3.2 HDB3 Codecs......................................................................................................11 3.3 HDB3 Decoder Alarms ........................................................................................12 3.4 Multiplexer ...........................................................................................................12 3.4.1 Flag Bits .................................................................................................13 3.4.2 Multiplexer Alarms ..................................................................................14 3.5 Demultiplexer ......................................................................................................14 3.5.1 Demultiplexer Alarms .............................................................................14 ...

Page 4

LXT6234 — E-Rate Multiplexer Tables 1 Input Signals ......................................................................................................... 7 2 Output Signals....................................................................................................... 9 3 Absolute Ratings ................................................................................................. Characteristics (TA=-40 to +85×C, Vdd=+5V±5%, GND=0 V)...................... 19 5 HDB3 Encoder and Decoder (Refer to 6 Multiplexer Tributary Input ...

Page 5

Block Diagram Figure 1. Block Diagram High Speed NRZ Data Input HDB3 Data Input 4 Tributary NRZ Data Inputs 4 HDB3 Pos/Neg Data Input Pairs 4 NRZ Data Inputs Service Channels / Ref Clock High Speed Multiplexer Clock NRZ ...

Page 6

... LXT6234 is the unique identifier for this product family. QE indicates the family member. Rev # Identifies the particular silicon “stepping” — refer to the specification update for additional stepping information. Lot # Identifies the batch. FPO # Identifies the Finish Process Order. 6 LXT6234QE XX XXXXXXXXXXXXXX XXXXXXXXX Definition 50 DHHDB3C 49 ...

Page 7

Table 1. Input Signals Pin # Sym HDB3 Decoder #1 Positive Data Input. HDB3 Decoder #1 positive rail input clocked on the positive 1 MLDPI1 transitions of the clock signal MLCK1. HDB3 Decoder #1 Negative Data Input. HDB3 Decoder #1 ...

Page 8

LXT6234— E-Rate Multiplexer Table 1. Input Signals (Continued) Pin # Sym National Bit Input. National Bit input that is placed in the 12th bit of the frame as per ITU G.742, G.751 36 MNAT specifications. AIS/Error Bit Input. AIS Bit ...

Page 9

Table 2. Output Signals Sym Pin # MLNRZO1 4 HDB3 Decoder #1 NRZ Output. HDB3 Decoder #1 NRZ output clocked on the rising edge of MLCK1. MLNRZO2 11 HDB3 Decoder #2 NRZ Output. HDB3 Decoder #2 NRZ output clocked on ...

Page 10

LXT6234— E-Rate Multiplexer Table 2. Output Signals (Continued) Sym Pin # HDB3 Encoder #1 Output -. HDB3 Encoder #1 negative rail output clocked out on the rising edge of DLDNO1 85 DLCI1. HDB3 Encoder #2 Output +. HDB3 Encoder #2 ...

Page 11

Functional Description The LXT6234 E-Rate Multiplexer consists of a multiplexer block, a demultiplexer block, five HDB3 decoders, and five HDB3 encoders. If the HDB3 codecs are used, the signal flow would be as follows: Multiplexer: Four tributaries of data ...

Page 12

LXT6234— E-Rate Multiplexer 3.3 HDB3 Decoder Alarms A Bipolar Violation Alarm (MLBPVx, DHBPV) associated with each HDB3 decoder indicate detection of a coding violation error within the data. Coding violations include Bipolar Violations, a string of more than four zeros ...

Page 13

In case of tributary transmission failure or the loss of a signal, tributary data can be forced to an all 1’s state. For each tributary this function is controlled at the MLFAISx pin. Figure 4. E2 Frame 213 217 J1 ...

Page 14

LXT6234— E-Rate Multiplexer 3.4.2 Multiplexer Alarms An indicator bit (MESAx) for each tributary monitors the status of the elastic store memory. This pin provides the justification status of the tributary. Under normal conditions this pin toggles at the frame rate ...

Page 15

Figure 6. Demultiplexer Side Block Diagram DHNRZI DHDMXC MODE DHDPI DHDNI DHHDB3C DLNRZI[1:4] 4 DLCI[1:4] Datasheet 4 DLNRZO[1:4] 4 DLCO[1:4] Demultiplexer And DNAT DAIS Timing 4 Control AUXO[1:4] DSYNC FLOS DHAISD DHNRZO HDB3 Decoder DHBPVO HDB3 4 4 DLDPO[1:4] ...

Page 16

LXT6234— E-Rate Multiplexer 4.0 Glossary AIS Alarm Indication Signal. AMI Alternate Mark Inversion. CCITT Consultative Committee for International Telegraph and Telephone (now called the International Telecommunications Union - ITU). CODEC COder/DECoder; An assembly comprising an encoder and a decoder within ...

Page 17

Application Information 5.1 E1/E3 Multiplexer Block Diagram Figure block diagram of the E1/E3 Multiplexer. Figure 7. E1/E3 Multiplexer Block Diagram MLCKx MHHDB3C DLCIx DHHB3C MLDPIx MLDNIx MHNRZI DHDPI DHDNI DLNRZIx MLNRZOx MLBPVx MHDPO MHDNO DHNRZO DHBPV ...

Page 18

LXT6234— E-Rate Multiplexer 5.1.3 LXT6234, E3 Stage • The multiplexer portion of the LXT6234 interleaves four asynchronous E2 rate NRZ data streams into a single E3 data stream. Depending on the configuration, either an on-board crystal oscillator or an external ...

Page 19

Test Specifications Note: Minimum and maximum values in Tables 3 through 9 and performance specifications of the LXT6234 E-Rate Multiplexer and are guaranteed by test except, where noted, by design. Typical values are not subject to production testing. The ...

Page 20

LXT6234— E-Rate Multiplexer 7.0 AC Timing Specifications Note: Unless otherwise specified, all timing specifications are referenced at ambient condition - Ambient Figure 8. HDB3 Encoder and Decoder Timing (Refer to Table 5) MLCKx ...

Page 21

Table 6. Multiplexer Tributary Input (Refer to Figure 9) Parameter Clock duty cycle Data to clock setup time (falling edge) Data to clock hold time (falling edge) Figure 10. High Speed Multiplexer Input & Output Timing (Refer to Table 7) ...

Page 22

LXT6234— E-Rate Multiplexer Figure 11. High Speed Demultiplexer Input & Output Timing (Refer to Table 8) DHDMXC DHNRZI DLNRZOx DLCOx DNAT/DAIS AUXOx Table 8. High Speed Demultiplexer Input & Output (Refer to Figure 11) Parameter Clock duty cycle Data to ...

Page 23

... Datasheet 100-Pin PQFP • Part Number LXT6234QE • Extended Temperature Range Table 10. 100-Pin Plastic Quad Flat Packs Inches Dim Min A – A 0.010 1 A 0.100 ...

Page 24

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