ISPLSI2192VE-100LT128 Lattice Semiconductor Corp., ISPLSI2192VE-100LT128 Datasheet
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ISPLSI2192VE-100LT128
Specifications of ISPLSI2192VE-100LT128
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ISPLSI2192VE-100LT128 Summary of contents
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... Interconnectivity • LEAD-FREE PACKAGE OPTIONS Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 2192VE Functional Block Diagram I/O I/O I/O I/O I RESET GOE 0 Generic Output Routing Pool (ORP) GOE 1 Logic Blocks (GLBs I I/O ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +5.4V cc Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION A Active ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f max (Ext.) – 4 ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f – 4 Clock Frequency ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic ...
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Power Consumption Power consumption in the ispLSI 2192VE device de- pends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 500 450 400 ...
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Signal Descriptions Signal Name RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of ...
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I/O Locations 128 144 Signal TQFP fpBGA Signal TQFP I I I I I I/O 52 I/O ...
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Pin Configuration ispLSI 2192VE 128-Pin TQFP Pinout Diagram I VCC I ...
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Signal Configuration ispLSI 2192VE 144-Ball fpBGA Signal Diagram I/O I/O A GND 59 61 I/O I/O B VCC 56 60 I/O I/O I I/O I/O I I/O I/O E ...
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Part Number Description ispLSI 2192VE Device Family Device Number Speed f 225 = 225 MHz max f 180 = 180 MHz max* f 135 = 135 MHz max f 100 = 100 MHz max *ispLSI 2192VE-225 recommended for new designs. ...