82547GI Intel Corporation, 82547GI Datasheet
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82547GI Summary of contents
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... Dual Footprint Design Guide Networking Silicon 317520-002 Revision 2.2 ...
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... North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708- 296-9333. Intel® trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © Intel Corporation, 2008 *Third-party brands and names are the property of their respective owners. ...
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... Updated reference schematics for signals EE_MODE and JTAG_TRST# (changed resistor values from 1 K Ω to 100 Ω). Updated sections 3.1.3, 3.1.1.8, and Table 5 in section 3.1.1 (changed max ESR rate from 20 Ω Ω for the 82547GI/EI). Updated reference schematics: sheets 4 and 6. Added Table 6; approved crystals for the 82547GI(EI). ...
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... Scope............................................................................................................................................ 1 1.2 Reference Documents .................................................................................................................. 2 1.3 Product Codes .............................................................................................................................. 2 2.0 System Data Port Interfaces .............................................................................................. 3 2.1 LCI Connection to 82562EZ(EX) Platform LAN Connect Device ................................................. 3 2.2 CSA Port Connection to 82547GI(EI) Gigabit Ethernet Controller ............................................... 4 2.2.1 Generation/Distribution of Reference Voltages ............................................................... 4 2.2.2 CSA Port Resistive Compensation .................................................................................. 5 3.0 Ethernet Component Design Guidelines ............................................................................ 7 3.1 General Design Considerations for Ethernet Controllers.............................................................. 7 3.1.1 Crystal Selection Parameters .......................................................................................... 7 3 ...
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... Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC Device....................... 29 4.3 Layout for the 82547GI(EI) Gigabit Ethernet Controller ............................................................. 30 4.3.1 Termination Resistors for Designs Based on 82547GI(EI) Gigabit Ethernet Controller 30 4.3.2 Light Emitting Diodes for Designs Based on 82547GI(EI) Controller ............................ 30 4.4 Physical Layer Conformance Testing ......................................................................................... 30 4.5 Troubleshooting Common Physical Layout Issues..................................................................... 31 5.0 Design and Layout Checklists ...
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... Memory Layout (512 Byte EEPROM) ..................................................................14 9 82562EZ(EX) Recommended Magnetics Modules.....................................................................14 10 Microwire Serial EEPROMs ...........................................................................................16 11 SPI Serial EEPROMs for 82547GI(EI) Controller .......................................................................16 12 82547GI(EI) EEPROM Memory Layout......................................................................................17 13 82547GI(EI) Recommended Magnetics Modules.......................................................................17 14 Ball Number to Signal Mapping ..................................................................................................35 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide ...
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... This application note contains Ethernet design guidelines applicable to LOM designs based on the ® Intel 865 Chipset and Intel between the 82562EZ(EX) Platform LAN Connect device and the 82547GI(EI) Gigabit Ethernet Controller. Section 2 describes the port interfaces specific to each device. Section 3 explains what you need to know to hook up an Ethernet device to the system. ...
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... I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Intel Corporation. Programming information can be obtained through your local Intel representative. 1.3 Product Codes Table 2 lists the product ordering codes for the 82562EZ(EX)and 82547GI(EI). Table 2. Product Ordering Codes Device 82562EZ GD82562EZ ...
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... System Data Port Interfaces The 82562EZ(EX) Platform LAN Connect Device and the 82547GI(EI) Gigabit Ethernet controller employ different system interfaces, as illustrated in GMCH CSA LCI Intel® ICH5 Figure 1. ICH5 Platform LAN Connect Sections 2.1 LCI Connection to 82562EZ(EX) Platform LAN Connect Device The 82562EZ(EX) Platform LAN Connect device uses the LAN Connect Interface (LCI) to connect to the I/O Control Hub 5 (ICH5) ...
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... Intel 2.2.1 Generation/Distribution of Reference Voltages The 11-bit CSA port on the 82547GI(EI) controller has a dedicated CI_VREF pin to sample the reference voltage. The nominal CSA port reference voltage is 0.35 V ± 3%. In addition to the reference voltage, a reference swing voltage, CI_SWING must be supplied to control buffer voltage swing characteristics. The nominal CSA port reference voltage swing must be 0.8 V ± ...
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... Table 4. CSA Port CI_RCOMP Resistor Values Component ® Intel 82547GI(EI) Figure 3. CSA port CI_RCOMP Circuits 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Figure 2) should be placed within 0.5 inches Figure Trace Impedance RCOMP Resistor Value 60 Ω ± 15 30.1 Ω ...
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... Ethernet Component Design Guidelines These sections provide recommendations for selecting components and connecting special pins. The main design elements are the 82562EZ(EX) Platform LAN Connect device or the 82547GI(EI) Gigabit Ethernet Controller, an integrated magnetics module with RJ-45 connector, and a crystal clock source. 3.1 General Design Considerations for Ethernet Controllers These recommendations apply to all designs, 10/100 or 10/100/1000 Mb/s ...
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... Dual Footprint Design Guide .Table 6 lists the approved crystals for use with the 83547GI(EI) B1 steppings. Table 6. 82547GI(EI) Recommended Crystals Raltron (<20 Ω ESR and +/-30 ppm) TXC 3.1.1.1 Vibration Mode Crystals in the frequency range listed in overtone. Unless there is a special need for third overtone, use fundamental mode crystals. ...
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... Figure 4 illustrates a simplified schematic of the 82562EZ(EX) and the 82547GI(EI) controller’s crystal circuit. The crystal and the capacitors form a feedback element for the internal inverting amplifier. This combination is called parallel-resonant, because it has positive reactance at the selected frequency ...
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... The lower the ESR, the faster the crystal starts up. Use crystals with an ESR value of 50 Ω or better. Note: Check the specific controller documentation carefully; some devices may have tighter ESR requirements. For example, Intel recommends that 82547GI(EI) devices use crystals with an ESR value of 10 Ω or less. 3.1.1.9 Drive Level Drive level refers to power dissipation in use ...
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... CLoad capacitance. Note: For 82547GI(EI) devices, Intel® recommends choosing a crystal with a ESR value of 10 Ω or less, an equivalent Cload of 18 pF, and a maximum of 30 ppm frequency shift. Cload is defined to be the load capacitance of the crystal, specified by the crystal vendor ...
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... Dual Footprint Design Guide 3.1.6 Integrated Magnetics Module The magnetics module has a critical effect on overall IEEE and regulatory conformance. The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation. Occasionally, components that meet basic specifications may cause the system to fail IEEE testing because of interactions with other components or the printed circuit board itself ...
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... Table 7 details on the EEPROM, refer to the appropriate I/O Control Hub and 7 EEPROM Map and Programming Information. Table 7. 82562EZ(EX) Memory Layout (128 Byte EEPROM) 00h 3Fh NOTE: No manageability provided. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 3.3Vstb 1K MMBT3904 1K 3.3Vstb LAN_RST# RST# RSMRST# ...
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... This section provides design guidelines specific to the 82547GI(EI) controller. 3.3.1 82547GI(EI) Ethernet Controller LAN Disable Guidelines The 82547GI(EI) Controller has a LAN_DISABLE# function that is present on FLSH_SO ball P9. This pin can be connected to a GPIO pin on the ICH5 component to allow the BIOS to disable the Ethernet port (see Figure serial output pin does not interfere with this function ...
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... Serial EEPROM for 82547GI(EI) Controller Implementations The 82547GI(EI) Gigabit Ethernet Controller can use either a Microwire SPI* serial EEPROM. The EEPROM mode is selected on the EEMODE input (ball C4). A pull-up resistor to Vcc denotes SPI*. A pull-down resistor to ground denotes Microwire. Several words of the EEPROM are accessed automatically by the device after reset to provide pre-boot configuration data before it is accessed by host software ...
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... V Microwire interface, serial EEPROM devices, with (or 256 x 16) organization and a 1 MHz speed rating. The 82547GI(EI)'s EEPROM access algorithm drives extra pulses on the shift clock at the beginnings and ends of read and write cycles. ...
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... A central power supply can provide all the required voltage sources, or the power can be derived and regulated locally near the Ethernet control circuitry. Keep in mind that all voltage sources must remain present during powerdown in order to use the 82547GI(EI) Ethernet controller's LAN wake up capability. This consideration makes it more likely that at least some of the voltage sources will be local ...
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... LAN address filters must also be set. The initial power management settings are specified by EEPROM bits. When the 82547GI(EI) controller transitions to either of the D3 low power states, the 1.2 V, 1.8 V, and 3.3 V sources must continue to be supplied to the device. Otherwise, it will not be possible to use a wakeup mechanism. The AUX_POWER signal is a logic input to the 82547GI(EI) controller that denotes auxiliary power is available ...
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... Device Test Capability The 82547GI(EI) Gigabit Ethernet Controller contains a test access port conforming to the IEEE 1149.1a-1994 (JTAG) Boundary Scan specification. To use the test access port, connect these balls to pads accessible by your test equipment. Be sure to connect the TRST# input to ground through a pull-down resistor (approximately 1k value) so that the test capability cannot be invoked by mistake ...
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... Since the transmission line medium extends onto the printed circuit board, special attention must be paid to layout and routing of the differential signal pairs. Designing for Gigabit operation is very similar to designing for 10 and 100 Mbps. For the 82547GI(EI) Gigabit Ethernet controller, system level tests should be performed at all three speeds. 4.1.1 Guidelines for Component Placement Component placement can affect signal quality, emissions, and component operating temperature ...
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... Dual Footprint Design Guide Keep silicon traces at least 1 inch from edge of PCB (2 inches preferred) LAN Silicon Figure 5. General Placement Distances Figure 5 shows some basic placement distance guidelines. The figure shows two differential pairs, but can be generalized for a Gigabit system with four analog pairs. The ideal placement for the Ethernet silicon would be approximately one inch behind the magnetics module ...
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... Do not route traces and vias under crystals or oscillators. This will prevent coupling to or from the clock. And as a general rule, place traces from clocks and drives at a minimum distance from apertures by a distance that is greater than the largest aperture dimension. Figure 6. Trace Routing 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 45° 45° Figure 6 ...
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... Dual Footprint Design Guide • The reference plane for the differential pairs should be continuous and low impedance recommended that the reference plane be either ground or 1.8 V (the voltage used by the PHY). This provides an adequate return path for and high frequency noise currents. ...
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... Power and Ground Planes Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly reduce EMI radiation. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 25 ...
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... Dual Footprint Design Guide The following guidelines help reduce circuit inductance in both backplanes and motherboards: • Route traces over a continuous plane with no interruptions. Do not route over a split power or ground plane. If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This will increase inductance and EMI radiation levels. • ...
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... C1, C2, C5, C6 The placement of C1 – C6 may also be different for each board design (i.e., not all of the capacitors may need to be populated). Also, the capacitors may not be needed on both sides of the magnetic module. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide RJ/Mag. RJ Shield connected to ...
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... Dual Footprint Design Guide 4.1.13 Special Considerations for Non-Integrated Magnetics Modules and RJ-45 Connectors It is possible to employ discrete (non-integrated) magnetics modules and RJ-45 connectors. Similar rules will apply to design and layout. The differential pairs should be routed short and symmetrical as possible and the overall lengths of the differential pairs (including the width of the magnetics module) should not exceed approximately four inches ...
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... Since LEDs are likely to be integral to a magnetics module, take care to route the LED traces away from potential sources of EMI noise. In some cases, it may be desirable to attach filter capacitors. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Figure Intel LAN device Place termination resistors as close to the Intel LAN device as possible ...
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... Ethernet Controller The four differential pairs are terminated with 49.9 Ω (1% tolerance) resistors, placed near the 82547GI(EI) controller. One resistor connects to the MDI+ signal trace and another resistor connects to the MDI- signal trace. The opposite ends of the resistors connect together and to ground through a single 0.1 µF capacitor. The capacitor should be placed as close as possible to the 49.9 Ω ...
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... Mbps rise and fall time. This will also cause return loss to fail at higher frequencies and will degrade the transmit BER performance capacitor is used, it should almost certainly be less than 22 pF. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 31 ...
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... Design and Layout Checklists The Design and Layout checklists are in Portable Data Format (PDF) and available to aid designers via: http://developer.intel.com. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 33 ...
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... VSS VSS VSS VSS RST# B10 NC SMB_ALERT# 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Signal Name 82562EZ(EX) Pop Option Difference? Connection? Required ...
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... Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Ref Pin Name Name B11 SPDLED# LED2/LINK100# B12 TOUT LED3/LINK1000# B13 RBIAS100 CTRL18 B14 RBIAS10 IEEE_TEST EEMODE C5 NC ...
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... VSS VSS F5 VSS VSS F6 VSS VSS F7 VSS VSS F8 VSS VSS F9 VSS VSS F10 VSS VSS 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Signal Name 82562EZ(EX) Pop Option Difference? Connection? Required ...
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... Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Ref Pin Name Name F11 VSS VSS F12 NC NC F13 NC MDI[2]+ F14 NC MDI[2 CI_CLK G2 NC CI[ CSA_1.2V G5 VCCR 1 VCC 1 ...
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... K12 VSS ANALOG_VSS K13 VCC 3.3 V K14 X1 XTAL1 L1 NC CI_STRS L2 NC CI_STRF L3 NC CI[4] L4 VCC 1 VCC 1 VSS VSS 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Signal Name 82562EZ(EX) Pop Option Difference? Connection? Required ...
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... Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Ref Pin Name Name L7 ADV10 VCC 1.2 V L10 VCC 1.2 V L11 VSS VSS L12 NC JTAG_TMS L13 JTXD[1] JTAG_TRST# L14 JTXD[2] JTAG_TCK M1 NC CI[ ...
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... P7 NC EECS P8 VSS VSS P9 NC FLSH_SO/ LAN_DISABLE# P10 NC EEDI P11 NC CTRL12 P12 3.3 V 3.3 V P13 JRXD[0] SDP[1] P14 NC NC 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Signal Name 82562EZ(EX) Pop Option Difference? Connection? Required ...
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... Dual Footprint Reference Schematic The following pages illustrate a dual purpose 10/100 and 10/100/1000 design using the 82562EZ(EX) Platform LAN Connect device and the 82547GI(EI) Gigabit Ethernet Controller. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 43 ...
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... Dual Footprint Design Guide 46 Pins VDD Pins VSS ...
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... Tektronix P6246, or similar high bandwidth, low capacitance (less than 1 pF) probe • Tektronix 1103, or similar probe power supply or probe amplifier • BNC, 50-ohm coaxial cable (less than 6 feet long) • System with power supply and test software for the LAN circuit to be tested 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 51 ...
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... Dual Footprint Design Guide A.3 Indirect Probing Method The indirect probing test method is applicable foremost devices that support 100BASE-T. Since probe capacitance can load the reference crystal and affect the measured frequency, the preferred method is to use the indirect probing test method when possible. ...
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... Calculate the accuracy of the measured and averaged center frequency with respect to an ideal 125.0000 MHz reference frequency. where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 1. Given: The measured averaged center frequency is 124.99942 MHz (or 124,999,420 Hertz). FrequencyAccuracy ppm 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Figure 11. Devices”. FrequencyAccuracy ppm ( ) ( ...
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... Because probe capacitance can load the reference crystal affecting the measured frequency preferable to use a probe with less than 1 pF capacitance. Note: Direct probing is not recommended for the 82547GI(EI) LAN silicon. The probe should be connected between the X2 (or Xout) pin of the LAN device and a nearby ground ...
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... Determine the center reference frequency as accurately as possible. This can be done by taking different readings using the frequency counter and then calculating the average results of the readings. 6. Calculate the accuracy of the measured and averaged center frequency with respect to an ideal 25.0000 MHz reference frequency. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide Figure 12. 55 ...
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... Dual Footprint Design Guide where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 3. Given: The measured averaged center frequency is 24.99963 MHz (or 24,999,630 Hertz). FrequencyAccuracy ppm Example 4. Given: The measured averaged center frequency is 25.00027 MHz (or 25,000,270 Hertz). FrequencyAccuracy ppm Note: The following items should be noted for an ideal reference crystal on a typical printed circuit board ...
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... Appendix B GigConf.exe Register Settings for 82547GI(EI) Devices The following steps describe the indirect probing test method using GigConf.exe for 82547GI(EI) devices. 1. Boot to DOS using a DOS Boot Diskette. 2. Launch Gigconf from the diskette (gigconf.exe). 3. Select the Intel network connection to be measured multiple adapters are installed, use the arrow keys to navigate to highlight the selected adapter and press Enter. 4. Select Registers by pressing “ ...
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