PXA255 Intel Corporation, PXA255 Datasheet
PXA255
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PXA255 Summary of contents
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... Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Product Features High Performance Processor I — Intel® XScale™ Microarchitecture — Instruction Cache — Data Cache — “mini” Data Cache — Extensive Data Buffering Intel® Media Processing Technology I — ...
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... The PXA255 processor EMTS Data Sheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... PXA255 Processor — Electrical, Mechanical, and Thermal Specification Contents 1.0 About This Document ............................................................................................ 7 2.0 Functional Overview ..............................................................................................7 3.0 Package Information ..............................................................................................8 3.1 Package Introduction..................................................................................... 8 3.1.1 3.2 Package Power Ratings ..............................................................................22 4.0 Electrical Specifications ...................................................................................... 22 4.1 Absolute Maximum Ratings......................................................................... 22 4.2 Power Consumption Specifications ............................................................. 23 4.3 Operating Conditions................................................................................... 25 4.4 Targeted DC Specifications......................................................................... 26 4.5 Targeted AC Specifications ......................................................................... 27 4.6 Oscillator Electrical Specifications............................................................... 28 4.6.1 4.6.2 4.7 Reset and Power AC Timing Specifications ................................................30 4 ...
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... Related Documentation......................................................................................... 7 2 Processor Pin Types ............................................................................................. 9 3 Pin and Signal Descriptions for the PXA255 Processor........................................ 9 4 Pin Description Notes.......................................................................................... 18 5 PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order .... 20 6 and Maximum Power Ratings........................................................................ 22 θ Absolute Maximum Ratings ................................................................................ 23 8 Power Consumption Specifications for PXA255 processor ................................ 24 9 Voltage, Temperature, and Frequency Electrical Specifications ...
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... PXA255 Processor — Electrical, Mechanical, and Thermal Specification Revision History Date Revision March 2003 February 2004 Data Sheet -001 First public release of the EMTS -002 Updated 400 MHz Idle mode power. Description 5 ...
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... PXA255 Processor — Electrical, Mechanical, and Thermal Specification 6 Data Sheet ...
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... A rich set of serial devices as well as general-system resources provide enough compute and connectivity capability for many applications. For details on the programming model and theory of operation of each of these units, refer to the Intel® PXA255 Processor Developer's Manual. For the processor block diagram, refer to Intel® ...
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... Functional Signal Definitions 3.1.1.1 PXA255 Processor Signal Pin Descriptions Table 3, “Pin and Signal Descriptions for the PXA255 Processor” on page 9 definitions for the PXA255 processor. physical characteristics of the PXA255 processor. 17x17mm mBGA Pinout — Ballpad No. Order” on page 20 processor. 8 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification ...
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... Analog Input OA Analog output IAOA Analog bidirectional SUP Supply pin (either VCC or VSS) Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet Pin Name Type Memory Controller Pins Memory address bus. (output) Signals the address MA[25:0] OCZ requested for memory accesses. ...
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... Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet Pin Name Type SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to the clock enable pins of SDCKE[1] OC SDRAM deasserted during sleep. SDCKE[1] is always de-asserted upon reset. The memory controller provides control register bits for de-assertion ...
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... Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet Pin Name Type LCD display data. (output) Transfers pixel information L_DD[15]/ from the LCD controller to the external LCD panel. ICOCZ GPIO[73] Memory controller grant. (output) Notifies an external device that it has been granted the system bus. ...
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... Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet Pin Name Type LCD display data. (output) Transfers pixel information L_DD[9]/ from the LCD controller to the external LCD panel. ICOCZ GPIO[67] MMC chip select 0. (output) Chip select 0 for the MMC controller ...
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... Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet Pin Name Type FFRI/ ICOCZ Full function UART ring indicator. (input) GPIO[38] FFDTR/ ICOCZ Full function UART data-terminal-ready. (output) GPIO[40] FFRTS/ ICOCZ Full function UART request-to-send. (output) GPIO[41] Bluetooth UART Pins ...
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... Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet Pin Name Type LCD display data. (output) Transfers pixel information L_DD[10]/ from the LCD controller to the external LCD panel. ICOCZ GPIO[68] MMC chip select 1. (output) Chip select 1 for the MMC controller ...
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... Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet Pin Name Type 2 AC97 Controller and I S Controller Pins AC97 audio port bit clock. (input) AC97 clock is generated by Codec 0 and fed into the PXA255 processor processor and Codec 1. AC97 Aaudio port bit clock. (output) AC97 clock is BITCLK/ generated by the PXA255 processor ...
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... Package Information Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet Pin Name Type TEXTAL IA 32 kHz crystal output. No external caps are required. LCD display data. (output) Transfers pixel information L_DD[12]/ from the LCD controller to the external LCD panel. ...
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... Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet Pin Name Type Reset out. (output) Asserted when nRESET is asserted and deasserts after nRESET is de-asserted but before nRESET_OUT OC the first instruction fetch. nRESET_OUT is also asserted for “soft” reset events: sleep, watchdog reset, or GPIO reset ...
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... See Section 3.5.9, “Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)” and Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8 in the Intel® PXA255 Processor Developers Manual. If selected as an input, this pin does not drive during sleep. If selected [ output, the value contained in the sleep-state register is driven out onto the pin and held there while the PXA255 processor is in sleep mode ...
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... Figure 2. PXA255 processor Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Package Information 19 ...
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... Package Information Table 5. PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order (Sheet Ball # Signal A1 VCCN A2 L_DD[13]/GPIO[71] A3 L_DD[12]/GPIO[70] A4 L_DD[11]/GPIO[69] A5 L_DD[9]/GPIO[67] A6 L_DD[7]/GPIO[65] A7 GPIO[11] A8 L_BIAS/GPIO[77] A9 SSPRXD/GPIO[26] A10 SDATA_OUT/GPIO[30] A11 SDA A12 FFDCD/GPIO[36] A13 FFRXD/GPIO[34] A14 FFCTS/GPIO[35] A15 ...
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... Table 5. PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order (Sheet Ball # Signal C5 L_DD[8]/GPIO[66] C6 VCCQ C7 L_DD[2]/GPIO[60] C8 VSSQ C9 BITCLK/GPIO[28] H12 TCK H13 TMS H14 GPIO[6] H15 TDI H16 TDO J1 MA[7] J2 VSSN J3 MA[6] J4 MD[18] J5 MA[5] J6 MA[4] J7 VCC J8 VSS J9 VSS J10 VSSQ J11 ...
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... Electrical Specifications Table 5. PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order (Sheet Ball # Signal K12 nBATT_FAULT K13 nVDD_FAULT K14 GPIO[3] K15 PXTAL K16 PEXTAL L1 MA[12] L2 VSSN L3 MA[13] L4 MD[20] L5 MD[2] L6 VCC L7 DQM[3] L8 MD[28] 3.2 Package Power Ratings Table 6. and Maximum Power Ratings θ ...
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... These figures are important when considering battery size and optimizing regulator efficiency. Typical systems operate with fewer modules active and at nominal voltage and load. The typical power consumption for the PXA255 processor is calculated using these conditions: • ...
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... Core operating at 98% instruction hit rate, 95% data hit rate, run mode • All voltages at nominal values • Nominal case temperature Table 8 contains power consumption numbers for the PXA255 processor. Table 8. Power Consumption Specifications for PXA255 processor (Sheet Symbol 400 MHz active mode, Maximum: V Typical: V =1.3V ccq I ...
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... Table 8. Power Consumption Specifications for PXA255 processor (Sheet Symbol I ccc I ccp P TOTAL Sleep mode, Maximum ccp Fast sleep wakeup mode, Maximum ccc I ccp 4.3 Operating Conditions This section shows voltage, frequency, and temperature specifications for the processor for four different ranges (shown in Specifications” ...
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... Output Low Current, all standard, high- IOL_H strength output and I/O pins (VO=VOH) Output Low Current, all standard, low- IOL_L strength output and I/O pins (VO=VOH) 26 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description Min 1.235 99.5 50 Table 10, “Standard Input, Output, and I/O Pin DC Operating ...
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... AC timings get with different loads. Input, Output, and I/O Pin AC Operating Conditions” high- and low-strength input, output, and I/O pins. All AC specification values are valid for the entire temperature range of the device. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description Min 0.9*VCCN ...
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... Stabilization Time Board Specifications RP_XT Parasitic Resistance, TXTAL/TEXTAL to any node CP_XT Parasitic Capacitance, TXTAL/TEXTAL, total COP_XT Parasitic Shunt Capacitance, TXTAL to TEXTAL 28 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description Table 13, “32.768-kHz Oscillator Specifications” Description Min Typical Max Units 10 ...
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... Float the PXTAL pin or drive it complementary to the PXTAL pin, with the same voltage level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility will be introduced in the system; therefore not recommended. Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Table 14 shows the 3.6864-MHz specifications. ...
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... On the processor important that the VCCQ power supply be powered up before or at the same time as the VCCN power supply. The VCC and PLL_VCC power supplies may be powered up anytime within the specification shown in 30 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification 31. Figure 3 and Table Figure 3, “ ...
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... Delay between VCC, PLL_VCC stable tD_NRESET and nRESET de-asserted Delay between nRESET de-asserted tD_OUT and nRESET_OUT de--asserted Delay between nRESET_OUT tD_NCS0 deasserted and nCS0 asserted Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification and nRESET timing requirements indicated in t R_VCCQ t R_VCCN t D_VCCN t ...
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... DHW_OUT_A Note: nBA TT_FAULT and nVDD_F AULT must be high before nRESET is deasserted Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is or the Cotulla will enter Sleep Mode de-asserted or the PXA255 processor enters sleep mode. Description 32. Section 4.6.1, “32.768-kHz Oscillator 28.) Figure 5, “GPIO Reset Timing” on page 33 ...
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... GPIO reset. The lock detector has a maximum time of 350µs plus synchronization. 4.7.5 Sleep Mode Timing Sleep mode is asserted internally; and asserts the nRESET_OUT and PWR_EN signals. The sequence indicated in Mode Timing Specifications” on page 34 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification t A_GP[1] xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx t ...
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... Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification t t D_PWR_R D_PWR_F Note: nBA TT_FAULT must be high or Cotulla will not exit Sleep Mode Note: nBATT_FAULT must be high or the PXA255 processor will not exit sleep mode. Description Min 91.6 61 30.5 28.0 — ...
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... RDY hold after nOE, nPWE de-asserted tvlioNPWE nPWE, nOE high time between beats of write or read data Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification (Table 20, “Variable Latency I/O Interface AC Specifications” on (Table 21, “Card Interface (PCMCIA or Compact 36) (Table 22, “Synchronous Memory Interface AC Specifications 1” on ...
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... MHz MEMCLK. It can be 99.5 MHz at the fastest. 3. This number represents 1/2 SDCLK period. 4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz MEMCLK at its fastest. 36 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Description 1 Description MEMCLKs ...
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... SSP Module AC Timing Figure 8, “SSP AC Timing Definitions” on page 38 pin timing specifications are referenced to SCLK_C. Values for the parameters are given in Table 24, “SSP AC Timing Specifications” on page Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification T pclkdv T pclklv T pclkbv T pclkfv Description ...
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... Input hold from TCK nTRST TBSOV1 TDO valid delay TOF1 TDO float delay TOV12 All outputs (non-test) valid delay 38 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification T sfmv T sfmv T rxds Description shows the boundary scan test signal timing. Parameter Min Max 0 ...
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... Input setup to TCK all inputs TIS10 (non-test) Input hold from TCK all inputs TIH8 (non-test) 4.10 AC Test Conditions The AC specifications load indicated in Figure 9. AC Test Load Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification Parameter Min Max 1.1 5.4 4.0 6.0 Section 4.5, “Targeted AC Specifications” on page 27 Figure 9. ...
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