HCTL-2020 Avago Technologies, HCTL-2020 Datasheet
HCTL-2020
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HCTL-2020 Summary of contents
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... HCTL-2000 Quadrature Decoder/Counter Interface ICs Data Sheet HCTL-2000, HCTL-2016, HCTL-2020 Description The HCTL-2000, 2016, 2020 are CMOS ICs that perform the quadrature decoder, counter, and bus interface function. The HCTL-20XX family is designed to improve system performance in digital closed loop motion control systems and digital data input systems. ...
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... The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL- 2000 contains a 12-bit counter. The HCTL-2016 and 2020 contain a 16-bit counter. The HCTL-2020 also contains quadrature decoder output Package Dimensions 19.05 0.25 (0.750 0.010) Operating Characteristics Table 1 ...
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Table 3. DC Characteristics Symbol Parameter [2] V Low-Level Input Voltage IL V [2] High-Level Input Voltage IH V Schmitt-Trigger Positive- T+ Going Threshold V Schmitt-Trigger Negative- T- Going Threshold V Schmitt-Trigger Hysteresis H I ...
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... CAS A pulse is presented on this LSTTL-compatible output when the HCTL-2020 internal counter overflows or underflows. The rising edge on this waveform may be used to trigger an external counter. These LSTTL-compatible tri-state outputs form an 8-bit output port through which the contents of the 12/16-bit position latch may be read in 2 sequential bytes ...
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Switching Characteristics Table 5. Switching Characteristics Min/Max specifications at V Symbol Description 1 t Clock period CLK 2 t Pulse width, clock high CHH [ Delay time, rising edge of clock to valid, updated count CD information on ...
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... Figure 4. Bus Control Timing. Figure 5. Decoder, Cascade Output Timing (HCTL-2020 only). 6 ...
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... Operation A block diagram of the HCTL- 20XX family is shown in Figure 6. The operation of each major function is described in the following sections. Figure 6. Simplified Logic Diagram. Digital Noise Filter The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. The input section uses two techniques to implement improved noise rejection ...
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... In the case of the HCTL-2020, the signals also go to external pins 5 and 16 respectively. Figure 9 shows the quadrature states and the valid state transi- tions ...
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... The HCTL-2016 or 2020 can be used in 16-bit mode and sampled at least once every 32,767 quadrature counts. D. The system count is > 16 bits so the HCTL-2020 can be cascaded with other stand- ard counter ICs to give absolute position. Position Data Latch The position data latch is a 12/ ...
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... See Figures 5 and 12 for detailed timing. Cascade Output (HCTL-2020 Only) The cascade output also consists of count and up/down outputs. When the HCTL-2020 internal counter overflows or underflows, a pulse, one-half clock cycle long, will be output on the CNT pin. CAS ...
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... For example, suppose the HCTL- 2020 count is at FFFFH and an external counter is at F0H, with the count going up. A count occurring in the HCTL-2020 will cause the counter to roll over and a cascade pulse will be generated. A read starting on this clock cycle will show FFFFH from the HCTL- 2020 ...
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... General Interfacing The 12-bit (HCTL-2000) or 16-bit (HCTL-2016/2020) latch and inhibit logic allows access bits of count with an 8-bit bus. When only 8-bits of count are required, a simple 8-bit (1- byte) mode is available by holding SEL high continuously. This disables the inhibit logic. OE provides control of the tri-state bus, and read timing is shown in Figures 2 and 3 ...
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Actions 1. On the rising edge of the clock, counter data is transferred to the position data latch, provided the inhibit signal is low. 2. When OE goes low, the outputs of the multiplexer are enabled onto the data lines. ...
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... Interfacing the HCTL-2020 to a Motorola 6802/8 and Cascading the Counter for 24 Bits Figure 14. A Circuit to Interface to the 6802/8. 14 ...
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... CAS the HCTL-2020 with the counter clock (CCK) input on both 74LS697s. The U/D pin on the HCTL-2020 and the U/D pin on both 74LS697s are also directly connected for easy expansion. The RCO of the first 4-bit 74LS697 is connected to the ENT pin of the second 74LS697. This ...
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... SEL to go low. When E goes high, the address decoder output for the HCTL-2020 OE signal goes low. This causes the HCTL-2020 to output the middle byte of the system counter (high byte of the HCTL-2020 counter). This middle byte, FFFFH is available at (2) through (4), the first time OE is low ...
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... Bits 0 and 1 of port 1 are used to control the OE and SEL inputs of the HCTL- 20XX respectively used to provide a clock signal to the HCTL-20XX. The frequency NOTE: PIN NUMBERS ARE DIFFERENT FOR THE HCTL-2020. Figure 17. An HCTL-20XX-to-Intel 8748 Interface. Object Source LOC Code ...
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... Avago sales representative for the following. M027 Interfacing the HCTL-20XX to the 8051 M019 Commonly Asked Questions about the HCTL- 2020 and Answers M020 A Simple Interface for the HCTL-2020 with a 16-bit DAC without Using a Processor M023 Interfacing the MC68HCII to the HCTL-2020 ...
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... For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5965-5894E 5988-5895EN June 2, 2006 www ...