LC74784 Sanyo Semiconductor Corporation, LC74784 Datasheet
LC74784
Available stocks
Related parts for LC74784
LC74784 Summary of contents
Page 1
... Preliminary Overview The LC74784 and LC74784M are on-screen display CMOS LSIs that display characters and patterns screen under microprocessor control. The LC74784 and LC74784M display lines of 24 characters, each dot matrix. Features • Display structure: 12 lines 288 characters) • Character structure: 12 (horizontal) 18 (vertical) dots • ...
Page 2
... Reset input Power supply (+ LC74784, 74784M Description Ground connection (digital system ground) Used to connect the crystal oscillator and capacitor used to generate the internal synchronization signal input an external clock (2fsc or 4fsc). Switches between external clock input mode and crystal oscillator mode. Low = crystal oscillator mode, high = external clock mode Outputs the blank signal (the OR of the character and border signals) ...
Page 3
... OSC F 1 OSC F 1 OSC F 1 OSC F 2 OSC Note: If the Xtal pin is used in clock input mode, be sure to prevent input noise from becoming a problem. IN LC74784, 74784M Symbol Conditions V max V 1 and V 2 pins max All pins IN V max BLANK, CHARA and SEP ...
Page 4
... Minimum input pulse width t W (CS (CS) Data setup time t SU (SIN (CS) Data hold time t h (SIN) t word One word write time t wt LC74784, 74784M unless otherwise specified DD Conditions CV pin IN CV pin OUT BLANK, CHARA and SEP pins 4.5 V, OUT –1 BLANK, CHARA and SEP pins ...
Page 5
... Serial Data Input Timing LC74784, 74784M No. 4991-5/15 ...
Page 6
... System Block Diagram LC74784, 74784M No. 4991-6/15 ...
Page 7
... LC74784/M locks into the display character data write mode, and another first byte cannot be written. When a high level is input to the CS pin, the LC74784/M is set to COMMAND0 (display memory write address setup mode). LC74784, 74784M ...
Page 8
... State 7 — — — Note: The register states are all set to zero when the LC74784/M is reset with the RST pin. COMMAND1 (Display character data write setup command) First byte DA0 to DA7 Register name State 7 — — — — — — — ...
Page 9
... Note: The register states are all set to zero when the LC74784/M is reset with the RST pin. COMMAND2 (Vertical display start position and vertical character size setup command) First byte DA0 to DA7 Register name State 7 — — — — VS21 VS20 VS11 ...
Page 10
... VP2 VP1 1 0 VP0 0 (LSB) 1 Note: The register states are all set to zero when the LC74784/M is reset with the RST pin. COMMAND3 (Horizontal display start position and horizontal character size setup command) First byte DA0 to DA7 Register name State 7 — — ...
Page 11
... DSPON 1 Note: The register states are all set to zero when the LC74784/M is reset with the RST pin. LC74784, 74784M Register content Function Command 4 identification code Display control Normal operating mode Test mode Erase display RAM (set to FF hexadecimal) Do not stop the crystal oscillator and LC oscillator circuits. ...
Page 12
... PH2 PH1 PH0 1 Note: The register states are all set to zero when the LC74784/M is reset with the RST pin. LC74784, 74784M Register content Function Command 5 identification code Display control NP0 0 NP1 0 NTSC 1 PAL Interlaced Non-interlaced External synchronization Internal synchronization Register content ...
Page 13
... RN1 RN0 SN3 SN2 SN1 SN0 1 Note: The register states are all set to zero when the LC74784/M is reset with the RST pin. COMMAND7 (Display control setup command) First byte DA0 to DA7 Register name State 7 — — — — EX1 PD1 ...
Page 14
... EGL 1 Note: The register states are all set to zero when the LC74784/M is reset with the RST pin. Display Screen Structure The display consists of 24 characters 12 rows. The maximum number of displayed character is 288. The maximum number of characters is reduced to less than 288 when the character size is enlarged. ...
Page 15
... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of Feburuary, 1997. Specifications and information herein are subject to change without notice. LC74784, 74784M output level waveform (V OUT DD ...
Page 16
Caption P.5 1. Serial to parallel converter 2. Character output dot clock generator 3. Sync separator 4. 8-bit latch + command decoder 5. Sync discriminator 6. Composite synchronizati on signal separator control 7. Horizontal character size register 8. Horizontal size ...
Page 17
NEW P.3 DIP24S, MFP24 P.6/15 Composite sync signal separator control 15/ ...