LC89960 Sanyo Semiconductor Corporation, LC89960 Datasheet
LC89960
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LC89960 Summary of contents
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... Ordering number : EN4544A Overview The LC89960 and LC89960M are delay lines and produce a 1H delayed signal for the NTSC format, with an external low-pass filter. Functions • 905-stage shift register • Auto-bias circuit • Sync tip clamp circuit • Sample-and-hold circuit • PLL 4 frequency multiplier circuit • ...
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... Supply voltage V DD Clock input amplitude V CLK Clock frequency F CLK Signal input amplitude V IN Note: * Since sync tip clamping is normally performed, the input signal must be connected in a low impedance state. Pin Assignment Block Diagram LC89960, 89960M Conditions Sine wave * Pin Functions Pin No ...
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... N O Output impedance Z O Delay time T D Note: 1. Input signal/output signal 2. Input signal/output signal LC89960, 89960M = 5.0 V, CLK = 3.579545 MHz; 500 mVp-p DD Conditions No signal input With a 200 kHz 0.5 Vp-p input 3.58 MHz, 0.2 Vp-p/200 kHz, 0.2 Vp signal input, the 4 fsc component No signal input, 0 ...
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... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provide information as of May, 1998. Specifications and information herein are subject to change without notice. LC89960, 89960M 1H delay output (positive phase) PS No. 4544-4/4 ...