LM49350RL/NOPB National Semiconductor, LM49350RL/NOPB Datasheet - Page 33
LM49350RL/NOPB
Manufacturer Part Number
LM49350RL/NOPB
Description
IC AUDIO SUBSYSTM 2W D 36USMDXT
Manufacturer
National Semiconductor
Series
Boomer®r
Type
Class Dr
Datasheet
1.LM49350RLNOPB.pdf
(104 pages)
Specifications of LM49350RL/NOPB
Output Type
1-Channel (Mono) with Mono and Stereo Headphones
Max Output Power X Channels @ Load
2W x 1 @ 4 Ohm; 69mW x 2 @ 32 Ohm
Voltage - Supply
2.7 V ~ 5.5 V
Features
3D, DAC, Depop, I²C, I²S, Mute, Short-Circuit and Thermal Protection, Shutdown, Volume Control
Mounting Type
Surface Mount
Package / Case
36-MicroSMDxt
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LM49350RLTR
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16.0 PMC Clocks Register
This register is used to control the LM49350's Basic Power Management Setup:
17.0 PMC Clock Divide Register
This register is used to control the LM49350's Power Management Circuits Clocks:
Bits
Bits
1:0
7:0
PMC_CLK_SEL
PMC_CLK_DIV
Field
Field
TABLE 4. PMC_SETUP (0x02h) (Default data value is 0x50h)
This selects the source of the PMC input clock.
This programs the half cycle divider that precedes the PMC. The PMC should run from a
300kHz clock. The default of this divider is 0x50h (divide by 40) to get a
from a 12MHz or 12.288MHz MCLK.
Program this divider with the division you want, multiplied by 2, and subtract 1.
TABLE 3. PMC_SETUP (0x01h)
PMC_CLK_SEL
PMC_CLK_DIV
00000000
00000001
00000010
00000011
00000100
00000101
11111101
11111110
11111111
00
01
10
11
—
33
Description
Description
MCLK (Default divide is 40)
Internal 300kHz Oscillator
PMC Input Clock Source
DAC SOURCE CLOCK
ADC SOURCE CLOCK
Divide by
127.5
126
128
1.5
2.5
—
1
1
2
3
≈
300kHz PMC clock
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