LMV1091TM/NOPB National Semiconductor, LMV1091TM/NOPB Datasheet - Page 8

• Manufacturer Part Number: LMV1091TM/NOPB
• Description: IC AMP MIC DUAL INPUT 25USMD
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Class ABr

Specifications of LMV1091TM/NOPB

• Output Type: 2-Channel (Stereo)
• Voltage - Supply: 2.7 V ~ 5.5 V
• Features: Differential Inputs, Microphone, Shutdown
• Mounting Type: Surface Mount
• Package / Case: 25-MicroSMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Max Output Power X Channels @ Load: -
• Other names: LMV1091TMTR

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Test Methods
FAR FIELD NOISE SUPPRESSION (FFNS
For optimum noise suppression the far field noise should be
in a broadside array configuration from the two microphones
(see Figure 8). Which means the far field sound source is
equidistance from the two microphones. This configuration
allows the amplitude of the far field signal to be equal at the
two microphone inputs, however a slight phase difference
may still exist. To simulate a real world application a slight
phase delay was added to the FFNS
from Figure 3 is used with the following procedure to measure
the FFNS
1.
2.
3.
4.
5.
NEAR FIELD SPEECH LOSS (NFSL
For optimum near field speech preservation, the sound
source should be in an endfire array configuration from the
A sine wave with equal frequency and amplitude
(25mV
generator, the phase of Mic 2 is delayed by 1.1° when
compared with Mic1.
Measure the output level in dBV (X)
Mute the signal from Mic2
Measure the output level in dBV (Y)
FFNS
E
E
.
P-P
= Y - X dB
) is applied to Mic1 and Mic2. Using a signal
E
test. The block diagram
E
)
FIGURE 2. FFNS
E
)
E
, NFSL
8
E
, SNRI
two microphones (see Figure 9). In this configuration the
speech signal at the microphone closest to the sound source
will have greater amplitude than the microphone further away.
Additionally the signal at microphone further away will expe-
rience a phase lag when compared with the closer micro-
phone. To simulate this, phase delay as well as amplitude
shift was added to the NFSL
3 is used with the following procedure to measure the NF-
SL
1.
2.
3.
4.
5.
SIGNAL TO NOISE RATIO IMPROVEMENT ELECTRICAL
(SNRI
The SNRI
E
.
A 25mV
applied to Mic1 and Mic2 respectively. Once again, a
signal generator is used to delay the phase of Mic2 by
15.9° when compared with Mic1.
Measure the output level in dBV (X)
Mute the signal from Mic2
Measure the output level in dBV (Y)
NFSL
E
E
SNRI
)
Test Circuit
E
E
is the ratio of FFNS
= Y - X dB
E
P-P
= FFNS
and 17.25mV
E
- NFSL
E
test. The schematic from Figure
P-P
E
E
(0.69*25mV
to NFSL
30092212
E
and is defined as:
P-P
) sine wave is