571BKA000105DG Silicon Laboratories Inc, 571BKA000105DG Datasheet

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571BKA000105DG

Manufacturer Part Number
571BKA000105DG
Description
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of 571BKA000105DG

Lead Free Status / Rohs Status
Compliant
10 MH
Features
Applications
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are
user-programmable to any output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz with <1 ppb resolution. The device is programmed
via an I
crystal is required for each output frequency, the Si57x uses one fixed-
frequency crystal and a DSPLL clock synthesis IC to provide any-frequency
operation. This IC-based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low-jitter clocks in noisy environments typically found in
communication systems.
Functional Block Diagram
Rev. 1.2 5/10
Any programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I
3rd generation DSPLL
jitter performance
3x better frequency stability than
SAW-based oscillators
SONET/SDH
xDSL
10 GbE LAN/WAN
2
SDA
C serial interface
OE
2
C serial interface. Unlike traditional XO/VCXOs where a different
V
Z TO
DD
Si571 only
V
Frequency
C
Fixed
XO
1.4 G H
ADC
®
with superior
DSPLL
10-1400 MHz
Synthesis
Copyright © 2010 by Silicon Laboratories
Clock
Z
Low-jitter clock generation
Optical modules
Clock and data recovery
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
I
2
C P
CLK-
GND
ROGRAMMABLE
CLK+
SCL
®
Si 570/Si 571
GND
GND
NC
OE
OE
Ordering Information:
V
C
Pin Assignments:
XO/VCXO
See page 24.
See page 23.
1
2
3
1
2
3
Si5602
(Top View)
Si570
Si571
SDA
SCL
SCL
SDA
7
8
7
8
6
5
4
6
5
4
Si570/Si571
V
CLK–
CLK+
V
CLK–
CLK+
DD
DD

Related parts for 571BKA000105DG

571BKA000105DG Summary of contents

Page 1

MH 1 Features  Any programmable output frequencies from 10 to 945 MHz and select frequencies to 1.4 GHz 2  serial interface ®  3rd generation DSPLL with superior jitter performance  ...

Page 2

Si570/Si571 2 Rev. 1.2 ...

Page 3

T C ABLE O F ONTENTS Section 1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Si570/Si571 1. Detailed Block Diagrams + RFREQ Frequency Control OE Control SDA Interface SCL NVM RAM Figure 1. Si570 Detailed Block Diagram + ADC V C VCADC RFREQ Frequency Control OE Control SDA Interface SCL NVM RAM Figure 2. Si571 ...

Page 5

Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current 2 Output Enable (OE) , Serial Data (SDA), Serial Clock (SCL) Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See Section "7. Ordering ...

Page 6

Si570/Si571 Table 3. CLK± Output Frequency Characteristics Parameter Symbol Programmable Frequency 1,2,3 Range 1,4 Temperature Stability Initial Accuracy Aging Total Stability 1,4 Absolute Pull Range 5 Power up Time Notes: 1. See Section "7. Ordering Information" on page 24 for ...

Page 7

Table 4. CLK± Output Levels and Symmetry Parameter Symbol LVPECL Output Option LVDS Output Option CML Output Option CMOS Output ...

Page 8

Si570/Si571 Table 6. CLK± Output Phase Jitter (Si571) Parameter Symbol  1,2,3 Phase Jitter (RMS) J for F > 500 MHz OUT Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter ...

Page 9

Table 6. CLK± Output Phase Jitter (Si571) (Continued) Parameter Symbol  2,4 Phase Jitter (RMS) J for 160 MHz OUT CMOS Output Only Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. ...

Page 10

Si570/Si571 Table 6. CLK± Output Phase Jitter (Si571) (Continued) Parameter Symbol  1,2,3 Phase Jitter (RMS) J for F of 125 to OUT 500 MHz Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. ...

Page 11

Table 8. Typical CLK± Output Phase Noise (Si570) Offset Frequency (f) 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Table 9. Typical CLK± Output Phase Noise (Si571) Offset Frequency (f) 100 Hz 1 kHz ...

Page 12

Si570/Si571 Table 11. Environmental Compliance The Si570/571 meets the following qualification test requirements. Parameter Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solder Heat Table 12. Programming Constraints and Timing (V = 3.3 V ±10 ...

Page 13

Functional Description The Si570 XO and the Si571 VCXO are low-jitter oscillators ideally suited for applications requiring programmable frequencies. The programmed to generate virtually any output clock in the range of 10 MHz to 1.4 GHz. Output jitter performance ...

Page 14

Si570/Si571 A typical frequency configuration for this example: RFREQ = 0x2EBB04CE0 current F = 148.35 MHz out_current F = 148.50 MHz out_new Calculate RFREQ to change the output frequency new from 148.35 MHz to 148.5 MHz:  RFREQ = 0x2EBB04CE0 ...

Page 15

Convert integer portion to a 10-bit binary number 0010 1110b 00 0010 1110 0000 1011 0000 0100 1100 1110 0000b Figure 4. Example of RFREQ Decimal to Hexadecimal Conversion Once the new values for RFREQ, HSDIV, and ...

Page 16

Si570/Si571 2 3. Interface The control interface to the Si570 2-wire bus for bidirectional communication. The bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both lines must be ...

Page 17

Serial Port Registers Note: Any register not listed here is reserved and must not be written. All bits are R/W unless otherwise noted. Register Name Bit 7 7 High Speed/ N1 Dividers 8 Reference N1[1:0] Frequency 9 Reference Frequency ...

Page 18

Si570/Si571 Register 7. High Speed/N1 Dividers Bit D7 D6 Name HS_DIV[2:0] Type R/W Bit Name 7:5 HS_DIV[2:0] DCO High Speed Divider. Sets value for high speed divider that takes the DCO output f 000 = 4 001 = 5 010 ...

Page 19

Register 9. Reference Frequency Bit D7 D6 Name Type Bit Name 7:0 RFREQ[31:24] Reference Frequency. Frequency control input to DCO. Register 10. Reference Frequency Bit D7 D6 Name Type Bit Name 7:0 RFREQ[23:16] Reference Frequency. Frequency control input to DCO. ...

Page 20

Si570/Si571 Register 12. Reference Frequency Bit D7 D6 Name Type Bit Name 7:0 RFREQ[7:0] Reference Frequency. Frequency control input to DCO. Register 135. Reset/Freeze/Memory Control Bit D7 D6 Name RST_REG NewFreq Type R/W R/W Reset settings = 00xx xx00 Bit ...

Page 21

Register 137. Freeze DCO Bit D7 D6 Name Type Reset settings = 00xx xx00 Bit Name 7:5 Reserved 4 Freeze DCO Freeze DCO. Freezes the DSPLL so the frequency configuration can be modified. 3:0 Reserved Freeze DCO ...

Page 22

Si570/Si571 5. Si570 (XO) Pin Descriptions Pin Name GND 4 CLK+ CLK– 5 (NC for CMOS*) (N/A for CMOS SDA 8 SCL *Note: CMOS output option only: make no external connection ...

Page 23

Si571 (VCXO) Pin Descriptions Pin Name GND 4 CLK+ CLK– 5 (NC for CMOS*) (N/A for CMOS SDA 8 SCL *Note: CMOS output option only: make no external connection ...

Page 24

Si570/Si571 7. Ordering Information The Si570/Si571 supports a wide variety of options including frequency range, start-up frequency, temperature stability, tuning slope, output format, and V at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. ...

Page 25

Si57x Mark Specification Figure 7 illustrates the mark specification for the Si57x. Table 15 lists the line information. Table 15. Si57x Top Mark Description Line Position 1 1–10 “SiLabs”+ Part Family Number, 5xx (First 3 characters in part number) ...

Page 26

Si570/Si571 9. Outline Diagram and Suggested Pad Layout Figure 8 illustrates the package details for the Si570/Si571. Table 16 lists the values for the dimensions shown in the illustration.   Figure 8. Si570/Si571 Outline Diagram Table 16. Package Diagram Dimensions ...

Page 27

PCB Land Pattern Figure 9 illustrates the 8-pin PCB land pattern for the Si570/Si571. Table 17 lists the values for the dimensions shown in the illustration. Figure 9. Si570/Si571 PCB Land Pattern Table 17. PCB Land Pattern Dimensions ...

Page 28

Si570/Si571 OCUMENT HANGE IST Revision 0.2 to Revision 0.3  Updated Table 1, “Recommended Operating Conditions,” on page 5. Device maintains stable operation over –40 to +85 ºC  operating temperature range. Supply current specifications updated.  ...

Page 29

N : OTES Si570/Si571 Rev. 1.2 29 ...

Page 30

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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