IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 40

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

Table-18 SLOS Criteria
3.5.3.2 System LOS (SLOS)
Dual Rail NRZ Format mode or in Dual Rail RZ Format mode.
side are monitored. When the input ‘0’s are equal to or more than N
consecutive pulse intervals, SLOS is declared. When the average
density of marks is at least 12.5% for M consecutive pulse intervals
starting with a mark, SLOS is cleared. Here N and M are defined by the
LAC bit (b7, LOS,...). Refer to Table-18 for details.
Functional Description
IDT82P2816
Note:
1. System input ports are schmitt-trigger inputs)
SLOS can only be detected when the transmit system interface is in
The amplitude and density of the data input from the transmit system
Operation
Mode
T1/J1
E1
LAC
0
1
0
1
ETSI 300233/
ANSI T1.231
ANSI I.431
Criteria
G.775
I.431
no pulse detected for N consecutive pulse intervals,
no pulse detected for N consecutive pulse intervals,
no pulse detected for N consecutive pulse intervals,
no pulse detected for N consecutive pulse intervals,
SLOS Declaring
N = 1544 bits
N = 2048 bits
N = 175 bits
N = 32 bits
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
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E1 mode, SLOS detection supports G.775 and ETSI 300233/I.431. The
criteria are selected by the LAC bit (b7, LOS,...).
transition from ‘0’ to ‘1’ on the SLOS_S bit (b1, STAT0,...) or any transi-
tion (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the SLOS_S bit (b1, STAT0,...) will
set the SLOS_IS bit (b1, INTS0,...) to ‘1’, as selected by the LOS_IES bit
(b1, INTES,...). When the SLOS_IS bit (b1, INTS0,...) is ‘1’, an interrupt
will be reported by INT if not masked by the SLOS_IM bit (b1, INTM0,...).
cated by the TMFn pin. Refer to Section 3.5.6 Error Counter and
Section 3.5.7.2 TMFn Indication respectively.
1
In T1/J1 mode, SLOS detection supports ANSI T1.231 and I.431. In
When SLOS is detected, the SLOS_S bit (b1, STAT0,...) will be set. A
SLOS may be counted by an internal Error Counter or may be indi-
12.5% mark density with less than 100 consecutive
12.5% mark density with less than 100 consecutive
12.5% mark density with less than 16 consecutive
12.5% mark density with less than 16 consecutive
zeros for M consecutive pulse intervals,
zeros for M consecutive pulse intervals,
zeros for M consecutive pulse intervals,
zeros for M consecutive pulse intervals,
SLOS Clearing
M = 175 bits
M = 175 bits
M = 32 bits
M = 32 bits
February 6, 2009
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