N28F001BXT150 Intel, N28F001BXT150 Datasheet - Page 18

• Manufacturer Part Number: N28F001BXT150
• Manufacturer: Intel

Specifications of N28F001BXT150

• Density: 1Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 17b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 128K
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

28F001BX
The entire sequence is performed with V
Abort occurs when RP# transitions to V
falls to V
is partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.
8.0 BOOT BLOCK PROGRAM AND
The boot block is intended to contain secure code
which will minimally bring up a system and control
programming and erase of other blocks of the
device, if needed. Therefore, additional “lockout”
protection is provided to guarantee data integrity.
Boot block program and erase operations are
enabled through high voltage V
OE#, and the normal Program and Erase command
sequences are used. Reference the AC waveforms
for program/erase.
If boot block program or erase is attempted while
RP# is at V
status bit will be set to “1”, reflective of the
operation being attempted and indicating boot block
lock. Program/erase attempts while V
V
attempted.
18
HH
produce spurious results and should not be
ERASE
PPL
, while erase is in progress. Block data
IH
, either the program status or erase
HH
on either RP# or
IH
PP
IL
< RP# <
at V
or V
PPH
PP
.
8.1
For on-board programming, the RP# pin is the most
convenient means of altering the boot block. Before
issuing Program or Erase Confirm commands, RP#
must transition to V
voltage throughout the program or erase interval
(until after status register confirmation of successful
completion). At this time, it can return to V
8.1.1
For PROM programming equipment that cannot
bring RP# to high voltage, OE# provides an
alternate boot block access mechanism. OE# must
transition to V
initial Program/Erase Setup command and held at
V
commands are issued to the device. After this
interval, OE# can return to normal TTL levels.
HH
at least 480 ns after Program or Erase Confirm
In-System Operation
PROGRAMMING EQUIPMENT
HH
a minimum of 480 ns before the
HH
. Hold RP# at this high
IH
or V
IL
.