N28F001BXT150 Intel, N28F001BXT150 Datasheet - Page 11

• Manufacturer Part Number: N28F001BXT150
• Manufacturer: Intel

Specifications of N28F001BXT150

• Density: 1Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 17b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 128K
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

Interface software to initiate and poll progress of
internal program and erase can be stored in any of
the 28F001BX blocks. This code is copied to, and
executed from, system RAM during actual flash
memory update. After successful completion of
program and/or erase, code execution out of the
28F001BX is again possible via the Read Array
command. Erase suspend/resume capability allows
system software to suspend block erase and read
data/execute code from any other block.
2.1
An on-chip state machine controls block erase and
byte program, freeing the system processor for
other tasks. After receiving the Erase Setup and
Erase Confirm commands, the state machine
controls block pre-conditioning and erase, returning
progress via the status register. Programming is
similarly controlled, after destination address and
expected data are supplied. The program algorithm
of past Intel Flash memories is now regulated by
the
repetition where required and internal verification
and margining of data.
2.2
Depending on the application, the system designer
may choose to make the V
switchable (available only when memory updates
are required) or hardwired to V
V
28F001BX command register architecture provides
protection from unwanted program
operations even when high voltage is applied to
V
whenever V
V
accommodates
encourages optimization of the processor-memory
interface.
The two-step program/erase write sequence to the
command register provides additional software
write protection.
PPL
PP
LKO
.
, memory contents cannot be altered. The
, or when RP# is at V
state
Additionally,
Command Register and Write
Automation
Data Protection
CC
machine,
is below the write lockout voltage
either
all
including
functions
design
IL
PP
PPH
. The 28F001BX
program
. When V
practice
power supply
are
or
disabled
erase
pulse
PP
and
=
3.0 BUS OPERATION
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
Figure 7. 28F001BX-B Memory Map
Figure 6. 28F001BX-T Memory Map
1DFFF
1CFFF
1FFFF
1BFFF
1FFFF
1E000
1D000
1C000
03FFF
02FFF
01FFF
00000
04000
03000
02000
00000
4-Kbyte Parameter Block
4-Kbyte Parameter Block
4-Kbyte Parameter Block
4-Kbyte Parameter Block
112-Kbyte Main Block
112-Kbyte Main Block
8-Kbyte Boot Block
8-Kbyte Boot Block
28F001BX
0406_06
0406_07
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