EPM7032STC44-5N Altera, EPM7032STC44-5N Datasheet - Page 8
EPM7032STC44-5N
Manufacturer Part Number
EPM7032STC44-5N
Description
51R9542
Manufacturer
Altera
Series
MAX 7000Sr
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7032STC44-5N
Cpld Type
EEPROM
No. Of Macrocells
32
No. Of I/o's
36
Propagation Delay
5ns
Global Clock Setup Time
2.9ns
Frequency
175.4MHz
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
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MAX 7000 Programmable Logic Device Family Data Sheet
Figure 2. MAX 7000E & MAX 7000S Device Block Diagram
8
INPUT/OE2/GCLK2
INPUT/GCLRn
INPUT/GCLK1
6 to 16 I/O Pins
6 to 16 I/O Pins
INPUT/OE1
Control
Control
Block
Block
I/O
I/O
6
6
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Figure 2
Logic Array Blocks
The MAX 7000 device architecture is based on the linking of high-
performance, flexible, logic array modules called logic array blocks
(LABs). LABs consist of 16-macrocell arrays, as shown in
Multiple LABs are linked together via the programmable interconnect
array (PIA), a global bus that is fed by all dedicated inputs, I/O pins, and
macrocells.
LAB A
LAB C
Macrocells
Macrocells
shows the architecture of MAX 7000E and MAX 7000S devices.
33 to 48
1 to 16
6 to16
6 to16
16
16
36
36
PIA
36
36
6 to16
6 to16
16
16
Macrocells
Macrocells
17 to 32
49 to 64
LAB D
LAB B
6 Output Enables
6 to16
6 to16
6 to16
6 to16
Control
Control
Block
Block
I/O
I/O
Altera Corporation
6
6
Figures 1
6 to 16 I/O Pins
6 to 16 I/O Pins
and 2.