XRP7714ILB-0X1C-F Exar Corporation, XRP7714ILB-0X1C-F Datasheet - Page 13
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XRP7714ILB-0X1C-F
Manufacturer Part Number
XRP7714ILB-0X1C-F
Description
IC CTRLR PWM/LDO STP-DWN 40TQFN
Manufacturer
Exar Corporation
Series
-r
Datasheet
1.XRP7714ILB-0X10-F.pdf
(29 pages)
Specifications of XRP7714ILB-0X1C-F
Topology
Step-Down (Buck) Synchronous (4), Linear (LDO) (1)
Function
Any Function
Number Of Outputs
5
Frequency - Switching
1.5MHz
Voltage/current - Output 1
Controller
Voltage/current - Output 2
Controller
Voltage/current - Output 3
Controller
W/led Driver
No
W/supervisor
No
W/sequencer
Yes
Voltage - Supply
4.75 V ~ 25 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1016-1698
For those using active 3.3V or 5V logic on the Enable pin an RC delay from VCCA to the Enable pin
may be used. When using an RC delay from VCCA, attention must be paid to the amount of
bypass capacitance loading AVDD since it will delay the time it takes for AVDD to power up and
regulate. The AVDD and DVDD pins do not require more than 2.2uF for proper bypassing. See
Figure 21 for the recommended components for sequencing the Enable pin through an RC delay
from VCCA.
increased. Once Enable is asserted, an internal CHIP_READY flag goes high and enables the I
acknowledge the Host’s serial commands. Channels that are configured as always-on channels are
enabled. Channels that are configured to be enabled by GPIOs are also enabled if the respective
GPIO is asserted.
In almost all cases, a simple check will ensure proper sequencing has been achieved. VCCA
regulates at approximately 4.6V when the Enable pin is logic level low and at 5.1V when Enable is
asserted. VCCA will typically power up and regulate before AVDD and because the internal logic is
not yet powered up there is no internal shutdown signal, it will regulate at 5.1V. Once AVDD has
reached sufficient voltage (and Enable is low) it will assert the internal shutdown signal and VCCA
will reduce its regulated voltage to 4.6V. When the Enable is asserted, the chip will power up and
VCCA will regulate at 5.1V. If our device is sequenced properly, VCCA will achieve 5.1V then drop
down to 4.6V and toggle back to 5.1V. See Figure 22 for an example.
© 2011 Exar Corporation
If more capacitance is added to AVDD and DVDD, the time constant must be
Fig. 21: RC Delay for Enable taken from VCCA
Fig. 22: VCCA (green) Startup Waveform
Q
Q
u
u
a
a
d
d
Enable Pin
C
C
h
h
a
a
13/29
n
n
n
n
e
e
l
l
VCCA
D
D
i
i
10K
.1uF
g
g
i
i
t
t
a
a
l
l
P
P
W
W
M
M
S
S
t
t
e
e
p
p
D
D
o
o
w
w
n
n
X
X
C
C
R
R
o
o
n
P
n
P
Rev. 1.1.6
t
t
7
7
r
r
o
o
7
7
2
l
l
C to
1
1
l
l
e
e
4
4
r
r