LFXP3E-4T100I Lattice, LFXP3E-4T100I Datasheet - Page 206
LFXP3E-4T100I
Manufacturer Part Number
LFXP3E-4T100I
Description
IC FPGA 3.1KLUTS 62I/O 100-TQFP
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP3E-4T100I
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number:
LFXP3E-4T100I
Manufacturer:
Lattice Semiconductor Corporation
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Figures 9-42 to 9-45 show the behavior of non-pipelined FIFO_DC or FIFO_DC without output registers. When we
pipeline the registers, the output data is delayed by one clock cycle. There is an extra option for output registers to
be enabled by the RdEn signal.
Figures 9-46 to 9-49 show similar waveforms for the FIFO_DC with output register and without output register
enable with RdEn. It should be noted that flags are asserted and de-asserted with similar timing to the FIFO_DC
without output registers. However it is only the data out ‘Q’ that is delayed by one clock cycle.
Figure 9-46. FIFO_DC With Output Registers, Start of Data Write Cycle
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
9-41
Invalid Q
Data_3
LatticeECP/EC and LatticeXP Devices
Data_4
Data_5
Memory Usage Guide
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